Memory cell including polarization retention member(s) including antiferroelectric layer over ferroelectric layer
Memory cells include various versions of a capacitor structure including a polarization retention member. Each polarization retention member includes an antiferroelectric layer over a ferroelectric layer. The antiferroelectric layer, among other layers, can be tailored to customize the hysteresis loop shape, and the coercive electric field required to change polarization of the memory cell. Metal electrodes, and/or dielectric or metallic interlayers may also be employed to tailor the hysteresis. The memory cells can include FeRAMs or FeFETs. The memory cells provide a lower coercive electric field requirement compared to conventional ferroelectric memory cells, enhanced reliability, and require minimum changes to integrate into current integrated circuit fabrication processes.
1. A memory cell, comprising:
a capacitor structure including:
a first electrode;
at least a pair of polarization retention members over the first electrode, each polarization retention member including an antiferroelectric layer over and in contact with a ferroelectric layer; and
a first metal electrode over and in contact with an uppermost one of the antiferroelectric layer.
2. The memory cell of claim 1 , wherein the first electrode includes a channel region between a source region and a drain region in a semiconductor substrate; and
wherein the at least a pair of polarization retention members are part of a gate stack over a first insulator layer over and in contact with the channel region.
3. The memory cell of claim 2 , further comprising a second metal electrode between a lowermost ferroelectric layer and the first insulator layer.
4. The memory cell of claim 1 , wherein the first electrode includes a metal electrode.
5. The memory cell of claim 1 , wherein the ferroelectric layer includes a dopant selected from a group comprised of: silicon (Si), aluminum (Al), lanthanum (La), nitrogen (N), strontium (Sr), gadolinium (Gd), yttrium (Y), or combinations thereof.
6. The memory cell of claim 1 , wherein the ferroelectric layer and the antiferroelectric layer are selected from a group comprised of: hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), hafnium zirconium oxide (Hf 0.5 Zr 0.5 O 2 ), lead zirconate titanate (PbZr/TiO 3 )(PZT), barium titanate (BaTiO 3 )(BTO), lead(II) titanate (PbTiO 3 ), or combinations thereof, and
wherein the ferroelectric layer and the antiferroelectric layer are different.
7. The memory cell of claim 6 , wherein at least one of the ferroelectric layer and the antiferroelectric layer includes a dopant selected from a group comprised of: silicon (Si), aluminum (Al), lanthanum (La), nitrogen (N), strontium (Sr), gadolinium (Gd), yttrium (Y), or combinations thereof.
8. The memory cell of claim 7 , wherein the antiferroelectric layer includes at least one of: a higher dopant concentration than the ferroelectric layer; a higher mechanical stress than the ferroelectric layer; a thinner thickness than the ferroelectric layer; and where the ferroelectric layer includes zirconium, a higher zirconium (Zr) content than the ferroelectric layer.
9. A memory cell, comprising:
a capacitor structure including:
a first electrode;
at least one polarization retention member over the first electrode, each polarization retention member including an antiferroelectric layer over and in contact with an interlayer over and in contact with a ferroelectric layer; and
a first metal electrode over and in contact with an uppermost one of the antiferroelectric layer.
10. The memory cell of claim 9 , wherein the first electrode includes a channel region between a source region and a drain region in a semiconductor substrate; and
wherein the at least one polarization retention member is part of a gate stack over an insulator layer over and in contact with the channel region.
11. The memory cell of claim 10 , further comprising a second metal electrode between a lowermost ferroelectric layer and the insulator layer.
12. The memory cell of claim 10 , wherein the insulator layer is selected from a group comprised of: silicon oxide (SiO 2 ), silicon oxynitride (SiON), silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), or hafnon (HfSiO 4 ).
13. The memory cell of claim 9 , wherein the first electrode includes a metal electrode.
14. The memory cell of claim 9 , wherein the interlayer has a thickness in a range of 0.5 Angstroms (Å) to 0.7 Å.
15. The memory cell of claim 9 , wherein the interlayer includes one of:
a dielectric interlayer selected from a group comprised of: titanium oxide (TiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ); and
a metallic interlayer selected from a group comprised of: titanium nitride (TiN), and tantalum nitride (TiN), aluminum (Al), hafnium (Hf), lanthanum (La).
16. The memory cell of claim 9 , wherein the ferroelectric layer and the antiferroelectric layer are selected from a group comprised of: hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), hafnium zirconium oxide (Hf 0.5 Zr 0.5 O 2 ), lead zirconate titanate (PbZr/TiO 3 )(PZT), barium titanate (BaTiO 3 )(BTO), lead(II) titanate (PbTiO 3 ), or combinations thereof,
wherein at least one of the ferroelectric layer and the antiferroelectric layer includes a dopant selected from a group comprised of: silicon (Si), aluminum (Al), lanthanum (La), nitrogen (N), strontium (Sr), gadolinium (Gd), yttrium (Y) or combinations thereof, and
wherein the ferroelectric layer and the antiferroelectric layer are different.
17. The memory cell of claim 16 , wherein the antiferroelectric layer includes at least one of: a higher dopant concentration than the ferroelectric layer; a higher mechanical stress than the ferroelectric layer; a thinner thickness than the ferroelectric layer; and where the ferroelectric layer includes zirconium, a higher zirconium (Zr) content than the ferroelectric layer.
18. A ferroelectric field effect transistor (FeFET), comprising:
a source region and a drain region in a semiconductor substrate;
a gate stack including:
a first insulator layer over and in contact with the semiconductor substrate between the source region and the drain region,
at least one polarization retention member over the first insulator layer, each polarization retention member including an uppermost antiferroelectric layer, a ferroelectric layer and a first metal electrode; and
a second metal electrode over and in contact with the uppermost antiferroelectric layer.
19. The FeFET of claim 18 , wherein the first metal electrode is in between and in contact with the uppermost antiferroelectric layer and the ferroelectric layer.
20. The FeFET of claim 18 , wherein the ferroelectric layer is under and in contact with the uppermost antiferroelectric layer and the first metal electrode is under and in contact with the ferroelectric layer.