Techniques for configuring a processor to function as multiple, separate processors

1. A computer-implemented method, comprising:

generating a first signal to sample performance data for a plurality of engines included in a processor, wherein the performance data is captured by a plurality of performance monitors;

receiving, based on the first signal, the performance data from the plurality of performance monitors, wherein the performance data includes a first identifier that identifies which performance monitor included in the plurality of performance monitors that generated the performance data;

extracting a plurality of performance data subsets from the performance data based on a plurality of second identifiers included in the performance data, wherein a first performance data subset of the plurality of performance data subsets includes the first identifier, wherein each of the plurality of performance data subsets corresponds to a different second identifier included in the plurality of second identifiers, and wherein each of the plurality of second identifiers corresponds to a different engine included in the plurality of engines; and

storing each of the plurality of performance data subsets in a different one of a plurality of data stores, wherein, for each of the plurality of performance data subsets, the different one of the plurality of data stores is determined based on the second identifier included in the performance data subset, wherein each data store included in the plurality of data stores is isolated from access by the plurality of engines other than a corresponding engine included in the plurality of engines, and wherein each engine in the plurality of engines accesses the corresponding data store in the plurality of data stores via a different virtual address space.

2. The computer-implemented method of claim 1 , wherein each data store included in the plurality of data stores is inaccessible to all other engines included in the plurality of engines.

3. The computer-implemented method of claim 1 , further comprising:

extracting a portion of the performance data that is not traceable to any engine included in the plurality of engines; and

storing the portion of the performance data that is not traceable to any engine in a first data store.

4. The computer-implemented method of claim 3 , wherein the first data store is accessible to an authorized entity associated with the processor and inaccessible to all engines included in the plurality of engines.

5. The computer-implemented method of claim 1 , wherein generating the first signal to sample the performance data comprises:

transmitting the first signal to an array of signal counters included in a first performance monitor included in the plurality of performance monitors; and

sampling, via the array of signal counters, at least a portion of the performance data.

6. The computer-implemented method of claim 1 , wherein generating the first signal to sample the performance data comprises:

combining one or more signals received by a first performance monitor included in the plurality of performance monitors according to a logical signal expression;

determining that a condition of the logical signal expression is met;

in response, transmitting the first signal to an array of signal counters included in the first performance monitor; and

sampling, via the array of signal counters, at least a portion of the performance data.

7. The computer-implemented method of claim 1 , wherein the performance data is based on a first signal group received via a first multiplexor.

8. The computer-implemented method of claim 7 , wherein the performance data is further based on a second signal group received via a second multiplexor.

9. A non-transitory computer-readable medium storing program instructions that, when executed by a processor, cause the processor to perform the steps of:

generating a first signal to sample performance data for a plurality of engines included in a processor, wherein the performance data is captured by a plurality of performance monitors;

receiving, based on the first signal, the performance data from the plurality of performance monitors, wherein the performance data includes a first identifier that identifies which performance monitor included in the plurality of performance monitors that generated the performance data;

extracting a plurality of performance data subsets from the performance data based on a plurality of second identifiers included in the performance data, wherein a first performance data subset of the plurality of performance data subsets includes the first identifier, wherein each of the plurality of performance data subsets corresponds to a different second identifier included in the plurality of second identifiers, and wherein each of the plurality of second identifiers corresponds to a different engine included in the plurality of engines; and

storing each of the plurality of performance data subsets in a different one of a plurality of data stores, wherein, for each of the plurality of performance data subsets, the different one of the plurality of data stores is determined based on the second identifier included in the performance data subset, wherein each data store included in the plurality of data stores is isolated from access by the plurality of engines other than a corresponding engine included in the plurality of engines, and wherein each engine in the plurality of engines accesses the corresponding data store in the plurality of data stores via a different virtual address space.

10. The non-transitory computer-readable medium of claim 9 , wherein generating the first signal to sample the performance data comprises:

transmitting the first signal to an array of signal counters included in a performance monitor; and

sampling, via the array of signal counters, at least a portion of the performance data.

11. The non-transitory computer-readable medium of claim 9 , wherein generating the first signal to sample the performance data comprises:

combining one or more signals received by a performance monitor according to a logical signal expression;

determining that a condition of the logical signal expression is met;

in response, transmitting the first signal to an array of signal counters included in the performance monitor; and

sampling, via the array of signal counters, at least a portion of the performance data.

12. The non-transitory computer-readable medium of claim 9 , wherein the performance data is based on a first signal group received via a first multiplexor.

13. The non-transitory computer-readable medium of claim 12 , wherein the performance data is further based on a second signal group received via a second multiplexor.

14. The non-transitory computer-readable medium of claim 9 , wherein the performance data is based on a first performance monitor associated with a first clock signal domain and a second performance monitor associated with a second clock signal domain.

15. The non-transitory computer-readable medium of claim 9 , wherein the performance data is associated with a duration of time between the first signal and a second signal to sample the performance data for the plurality of engines.

16. The non-transitory computer-readable medium of claim 15 , wherein the first signal coincides with a first context switch event associated with a first engine and the second signal coincides with a second context switch event associated with the first engine.

17. A system, comprising:

a memory storing a software application; and

a processor that, when executing the software application, is configured to perform the steps of:

generating a first signal to sample performance data for a plurality of engines included in the processor, wherein the performance data is captured by a plurality of performance monitors, wherein the performance data includes a first identifier that identifies which performance monitor included in the plurality of performance monitors that generated the performance data;

causing one or more performance monitors to capture the performance data based on the first signal;

receiving the performance data from the plurality of performance monitors;

extracting a plurality of performance data subsets from the performance data based on a plurality of second identifiers included in the performance data, wherein a first performance data subset of the plurality of performance data subsets includes the first identifier, wherein each of the plurality of performance data subsets corresponds to a different second identifier included in the plurality of second identifiers, and wherein each of the plurality of second identifiers corresponds to a different engine included in the plurality of engines; and

storing each of the plurality of performance data subsets in a different one of a plurality of data stores, wherein, for each of the plurality of performance data subsets, the different one of the plurality of data stores is determined based on the second identifier included in the performance data subset, wherein each data store included in the plurality of data stores is isolated from access by the plurality of engines other than a corresponding engine included in the plurality of engines, and wherein each engine in the plurality of engines accesses the corresponding data store in the plurality of data stores via a different virtual address space.

18. The system of claim 17 , wherein the processor executes a plurality of virtual machines, and further comprising:

determining that no virtual machine included in the plurality of virtual machines is utilizing a first circuit subsection included in the processor; and

reducing a supply voltage associated with the first circuit subsection.

19. The system of claim 17 , wherein each circuit subsection included in a plurality of circuit subsections is associated with a different engine included in the plurality of engines, and further comprising:

determining that a first circuit subsection included in the plurality of circuit subsections is consuming more power than each of the other circuit subsections included in the plurality of circuit subsections; and

reducing a frequency of a clock signal associated with the first circuit subsection.