Metal-insulator-metal capacitor having electrodes with increasing thickness
View Patent ↗Disclosed are metal-insulator-metal capacitors and integrated chips. In one embodiment, a metal-insulator-metal capacitor includes N electrodes and (N−1) passivation layers, wherein the N electrodes and the (N−1) passivation layers are alternately stacked on a substrate. N is an integer larger than 1. Thicknesses of the N electrodes gradually increase in a direction parallel to a normal direction of the substrate.
1. A metal-insulator-metal capacitor, comprising:
N electrodes and (N−1) passivation layers, wherein the N electrodes and the (N−1) passivation layers are alternately stacked on a substrate, N is an integer larger than 2, the N electrodes comprise an m th electrode to an N th electrode sequentially arranged in a direction parallel to a normal direction of the substrate, m is 1 to N−1, a thickness of the m th electrode is smaller than a thickness of the N th electrode, the thickness of the m th electrode is less than or equal to a thickness of the m+1 th electrode, and wherein:
a first electrode among the N electrodes is disposed on the substrate,
a first passivation layer among the (N−1) passivation layers is disposed on the first electrode and the substrate, and the first passivation layer has a step region that continuously contacts and extends from a top surface of the first electrode to sidewalls of the first electrode, and
a second electrode among the N electrodes is disposed on the first passivation layer, and the second electrode has a step region that continuously contacts and extends from a top surface of the first passivation layer to sidewalls of the first passivation layer.
2. The metal-insulator-metal capacitor as claimed in claim 1 , wherein the m th electrode to the N th electrode are sequentially arranged in the normal direction of the substrate.
3. The metal-insulator-metal capacitor as claimed in claim 1 , wherein the m th electrode to the N th electrode are sequentially arranged in a direction opposite to the normal direction of the substrate.
4. The metal-insulator-metal capacitor as claimed in claim 1 , wherein N is 3 to 10.
5. The metal-insulator-metal capacitor as claimed in claim 1 , wherein the thicknesses of the N electrodes are 10 nm to 100 nm.
6. The metal-insulator-metal capacitor as claimed in claim 1 , wherein the thicknesses of the N electrodes are all different.
7. The metal-insulator-metal capacitor as claimed in claim 1 , wherein N is 5, two most distant electrodes among the N electrodes have different thicknesses, and at least two adjacent electrodes among the N electrodes have the same thickness.
8. An integrated chip, comprising:
an interconnect structure overlying a substrate; and
a metal-insulator-metal capacitor disposed on the interconnect structure and comprising:
N electrodes and (N−1) passivation layers, wherein the N electrodes and the (N−1) passivation layers are alternately stacked on the interconnect structure, N is an integer larger than 2, the N electrodes comprise an m th electrode to an N th electrode sequentially arranged in a direction parallel to a normal direction of the substrate, m is 1 to N−1, a thickness of the m th electrode is smaller than a thickness of the N th electrode, the thickness of the m th electrode is less than or equal to a thickness of the m+1 th electrode, and wherein:
a first electrode among the N electrodes is disposed on the substrate,
a first passivation layer among the (N−1) passivation layers is disposed on the first electrode and the substrate, and the first passivation layer has a step region that continuously contacts and extends from a top surface of the first electrode to sidewalls of the first electrode, and
a second electrode among the N electrodes is disposed on the first passivation layer, and the second electrode has a step region that continuously contacts and extends from a top surface of the first passivation layer to sidewalls of the first passivation layer.
9. The integrated chip as claimed in claim 8 , wherein the m th electrode to the N th electrode are sequentially arranged in the normal direction of the substrate.
10. The integrated chip as claimed in claim 8 , wherein the m th electrode to the N th electrode are sequentially arranged in a direction opposite to the normal direction of the substrate.
11. The integrated chip as claimed in claim 8 , wherein N is 3 to 10.
12. The integrated chip as claimed in claim 8 , wherein the thicknesses of the N electrodes are 10 nm to 100 nm.
13. The integrated chip as claimed in claim 8 , wherein the thicknesses of the N electrodes are all different.
14. The integrated chip as claimed in claim 8 , wherein N is 5, two most distant electrodes among the N electrodes have different thicknesses, and at least two adjacent electrodes among the N electrodes have the same thickness.
15. An integrated chip, comprising:
an interconnect structure overlying a substrate; and
a metal-insulator-metal capacitor disposed in the interconnect structure and comprising:
N electrodes and (N−1) passivation layers, wherein the N electrodes and the (N−1) passivation layers are alternately stacked in the interconnect structure, N is an integer larger than 2, the N electrodes comprise an m th electrode to an N th electrode sequentially arranged in a direction parallel to a normal direction of the substrate, m is 1 to N−1, a thickness of the m th electrode is smaller than a thickness of the N th electrode, the thickness of the m th electrode is less than or equal to a thickness of the m+1 th electrode, and wherein:
a first electrode among the N electrodes is disposed on the substrate,
a first passivation layer among the (N−1) passivation layers is disposed on the first electrode and the substrate, and the first passivation layer has a step region that continuously contacts and extends from a top surface of the first electrode to sidewalls of the first electrode, and
a second electrode among the N electrodes is disposed on the first passivation layer, and the second electrode has a step region that continuously contacts and extends from a top surface of the first passivation layer to sidewalls of the first passivation layer.
16. The integrated chip as claimed in claim 15 , wherein the m th electrode to the N th electrode are sequentially arranged in the normal direction of the substrate.
17. The integrated chip as claimed in claim 15 , wherein N is 3 to 10.
18. The integrated chip as claimed in claim 15 , wherein the thicknesses of the N electrodes are 10 nm to 100 nm.
19. The integrated chip as claimed in claim 15 , wherein the thicknesses of the N electrodes are all different.
20. The integrated chip as claimed in claim 15 , wherein N is 5, two most distant electrodes among the N electrodes have different thicknesses, and at least two adjacent electrodes among the N electrodes have the same thickness.