Substrate and package structure

1. A device comprising:

a substrate comprising:

first pads in a core area of the substrate;

second pads in a corner area of the substrate; and

third pads in an edge area of the substrate, the edge area extending around each side of the core area in a top-down view, a widest portion of the third pads having a lesser width than a widest portion of the first pads and a widest portion of the second pads in a cross-sectional view; and

a chip comprising bumps, each of the bumps having a substantially same width as the widest portion of the first pads and the widest portion of the second pads in the cross-sectional view, a first subset of the bumps connected to the first pads of the substrate, a second subset of the bumps connected to the second pads of the substrate, a third subset of the bumps connected to the third pads of the substrate.

2. The device of claim 1 , wherein a width of the core area is about 80% of a width of the substrate, and a length of the core area is about 80% of the length of the substrate.

3. The device of claim 1 further comprising:

solders, a first subset of the solders connecting the first subset of the bumps to the first pads, a second subset of the solders connecting the second subset of the bumps to the second pads, a third subset of the solders connecting the third subset of the bumps to the third pads.

4. The device of claim 3 , wherein each of the solders have a same width.

5. The device of claim 1 , wherein the bumps have a bump size, the first pads have a first pad size, and the second pads have a second pad size, wherein a ratio of the bump size to the first pad size is in a range of about 0.75 to about 1.25, and wherein a ratio of the bump size to the second pad size is in a range of about 0.75 to about 1.25.

6. The device of claim 5 , wherein the third pads have a third pad size, and a ratio of the bump size to the third pad size is about 0.5.

7. A device comprising:

a substrate comprising:

first pads in a core area of the substrate;

second pads in a corner area of the substrate; and

third pads in other areas in the substrate except the core area and the corner area; and

a chip comprising bumps, each of the bumps having a substantially same width as the first pads and the second pads, the bumps having a larger width than the third pads, a first subset of the bumps connected to the first pads of the substrate, a second subset of the bumps connected to the second pads of the substrate, a third subset of the bumps connected to the third pads of the substrate.

8. The device of claim 7 , wherein the third pads are in an edge area of the substrate, the edge area extending around the core area.

9. The device of claim 7 , wherein a width of the core area is about 80% of a width of the substrate, and a length of the core area is about 80% of the length of the substrate.

10. The device of claim 7 further comprising:

solders, a first subset of the solders connecting the first subset of the bumps to the first pads, a second subset of the solders connecting the second subset of the bumps to the second pads, a third subset of the solders connecting the third subset of the bumps to the third pads.

11. The device of claim 10 , wherein each of the solders have a same size.

12. The device of claim 7 , wherein the bumps have a bump size, the first pads have a first pad size, and the second pads have a second pad size, wherein a ratio of the bump size to the first pad size is in a range of about 0.75 to about 1.25, and wherein a ratio of the bump size to the second pad size is in a range of about 0.75 to about 1.25.

13. The device of claim 12 , wherein the third pads have a third pad size, and a ratio of the bump size to the third pad size is about 0.5.

14. A device comprising:

a substrate comprising:

first traces in a core area of the substrate, a center of the core area aligned to a center of the substrate, the first traces each having a first width and having a first length along a surface of the substrate, the first length greater than the first width; and

second traces in a non-core area of the substrate, the non-core area adjacent the core area, the second traces each having a second width and having a second length along the surface of the substrate, the second length greater than the second width, the second width less than the first width; and

a chip comprising bumps, each of the bumps having a same width, a first subset of the bumps connected to the first traces of the substrate, a second subset of the bumps connected to the second traces of the substrate.

15. The device of claim 14 , wherein the non-core area is an edge area of the substrate, the edge area extending around the core area.

16. The device of claim 14 , wherein a width of the core area is about 80% of a width of the substrate, and a length of the core area is about 80% of the length of the substrate.

17. The device of claim 14 further comprising:

solders, a first subset of the solders connecting the first subset of the bumps to the first traces, a second subset of the solders connecting the second subset of the bumps to the second traces.

18. The device of claim 17 , wherein each of the solders have a same width.

19. The device of claim 14 , wherein the bumps have a bump size, and the first traces have a first trace size, wherein a ratio of the bump size to the first trace size is in a range of about 0.75 to about 1.25.

20. The device of claim 19 , wherein the second traces have a second trace size, and a ratio of the bump size to the second trace size is about 0.5.