Gate-all-around integrated circuit structures fabricated using alternate etch selective material
Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
1. An integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires;
a gate stack over the vertical arrangement of horizontal nanowires, wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode;
a pair of dielectric spacers along sides of the gate stack and over the vertical arrangement of horizontal nanowires; and
a metal oxide material between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
2. The integrated circuit structure of claim 1 , wherein the metal oxide material is a metal oxide selected from the group consisting of titanium oxide (TiOx), tantalum oxide (TaOx) and aluminum oxide (A 10 x).
3. The integrated circuit structure of claim 1 , wherein the pair of dielectric spacers comprises a dielectric material selected from the group consisting of silicon nitride, silicon oxynitride, silicon oxide, and carbon-doped silicon nitride.
4. The integrated circuit structure of claim 1 , wherein the high-k gate dielectric layer comprises a metal oxide gate dielectric material different than the metal oxide material.
5. The integrated circuit structure of claim 1 , further comprising:
a pair of epitaxial source or drain structures at first and second ends of the vertical arrangement of horizontal nanowires.
6. The integrated circuit structure of claim 5 , wherein the pair of epitaxial source or drain structures is a pair of discrete epitaxial source or drain structures.
7. The integrated circuit structure of claim 5 , wherein the pair of epitaxial source or drain structures is a pair of non-discrete epitaxial source or drain structures.
8. The integrated circuit structure of claim 1 , wherein the vertical arrangement of horizontal nanowires is over a subfin, and the metal oxide material is further between the subfin and a bottommost nanowire of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
9. The integrated circuit structure of claim 8 , wherein the subfin comprises a portion of a bulk silicon substrate.
10. The integrated circuit structure of claim 1 , wherein the nanowires of the vertical arrangement of horizontal nanowires comprise silicon.
11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires;
a gate stack over the vertical arrangement of horizontal nanowires, wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode;
a pair of dielectric spacers along sides of the gate stack and over the vertical arrangement of horizontal nanowires; and
a metal oxide material between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
12. The computing device of claim 11 , further comprising:
a memory coupled to the board.
13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
15. The computing device of claim 11 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
16. The computing device of claim 11 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.