Vertical 1T-1C DRAM array
A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.
1. A method of forming an integrated circuit comprising:
forming transistor bodies in a plurality rows on a substrate, each of the bodies comprising a first diffusion region, a second diffusion region and a channel of a transistor, wherein the second diffusion regions is on the first diffusion region and separated by the channel;
forming a masking material as a plurality of rows across the bodies;
etching the bodies through the masking material to define a width dimension of the transistor bodies, wherein the width dimension is defined by a width dimension of the masking material;
after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units comprising the width dimension and a length dimension defined by the patterning; and
replacing each of the plurality of individual masking units with a programmable element.
2. The method of claim 1 , wherein forming the masking material as a plurality of rows comprises forming the plurality of rows of the masking material perpendicular to the plurality of rows of the transistor bodies.
3. The method of claim 1 , wherein the programmable element comprises a capacitor.
4. The method of claim 3 , wherein the capacitor comprises a metal-insulator- metal capacitor.
5. The method of claim 1 , wherein prior to replacing each of the plurality of individual masking units with a programmable element, the method comprises isolating the individual masking units with a dielectric material.
6. The method of claim 1 , wherein forming the bodies in a plurality of rows on a substrate comprises forming the bodies in a device layer of the substrate.
7. A method of fabricating a programmable array, the method comprising:
forming a plurality of cells aligned in a first row and a second row on a substrate, the second row parallel with and adjacent to the first row, wherein each of the plurality of cells comprises a programmable element and a transistor, wherein the transistor comprises a body, the body comprising a first diffusion region and a second diffusion region above the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region; and
forming a gate electrode coupled to the channel of each of the plurality of cells in the first row and the second row.
8. The method of claim 7 , wherein the programmable element of each of the plurality of cells comprises a capacitor.
9. The method of claim 8 , wherein the capacitor is a metal-insulator-metal capacitor.
10. The method of claim 7 , wherein the substrate comprises a device layer on the substrate and a plurality of metallization layers on the device layer and the plurality of cells are formed in the device layer.
11. The method of claim 7 , wherein the substrate comprises a device layer on the substrate and a plurality of metallization layers on the device layer.
12. The method of claim 11 , wherein the plurality of cells are disposed between ones of the plurality of metallization layers.
13. A method of fabricating an integrated circuit array apparatus, the method comprising:
forming a first plurality of cells aligned in a first row on a substrate, wherein each cell comprises a programmable element and a body comprising a first diffusion region, a second diffusion region and a channel of a transistor, wherein the second diffusion region is on the first diffusion region and separated by the channel; and
forming a second plurality of cells aligned in a second row on the substrate, the second row parallel with and adjacent to the first row, wherein each cell comprises a programmable element and a body comprising a first diffusion region, a second diffusion region and a channel of a transistor, wherein the second diffusion region is on the first diffusion region and separated by the channel, the second plurality of cells further comprising a gate stack coupled to one side of the channel, wherein the stack comprises a gate electrode comprising an indivisible body extending between each body of the second plurality of cells and coupled to a channel of each of the first plurality of cells as a second address line.
14. The method of claim 13 , wherein the programmable element of each of the first plurality of cells and the second plurality of cells comprises a capacitor.
15. The method of claim 14 , wherein the capacitor is a metal-insulator-metal capacitor.
16. The method of claim 13 , wherein the body of each of the first plurality of cells and the second plurality of cells projects in a direction perpendicular to a base surface of the substrate.
17. The method of claim 13 , wherein the substrate comprises a device layer on the substrate and a plurality of metallization layers on the device layer.
18. The method of claim 17 , wherein the first plurality of cells and the second plurality of cells are each formed in the device layer.
19. The method of claim 13 , wherein the substrate comprises a device layer on the substrate and a plurality of metallization layers on the device layer.
20. The method of claim 19 , wherein the first plurality of cells and the second plurality of cells are each disposed between ones of the plurality of metallization layers.