Semiconductor device including integrated capacitor and vertical channel transistor and methods of forming the same

1. A semiconductor device, comprising:

an insulating base including a trench;

a transistor comprising a gate electrode, a vertical channel in the trench, a drain electrode and a source electrode;

an isolation layer on the gate electrode in the trench; and

a capacitor comprising:

a trench capacitor portion comprising a lower conductive layer, wherein the trench capacitor portion is on the isolation layer formed within the trench; and

a stacked capacitor portion comprising a plurality of stacked conductive layers, wherein the stacked capacitor portion is coupled to the source electrode of the transistor formed outside the trench.

2. The semiconductor device of claim 1 , wherein the lower conductive layer extends outside the trench and is connected to the plurality of stacked conductive layers.

3. The semiconductor device of claim 1 , wherein the trench capacitor portion further comprises a lower dielectric layer on the lower conductive layer in the trench.

4. The semiconductor device of claim 3 , wherein the stacked capacitor portion further comprises an upper dielectric layer on the plurality of stacked conductive layers, and

wherein the lower dielectric layer extends outside the trench and is connected to the upper dielectric layer.

5. The semiconductor device of claim 4 , wherein the capacitor further comprises a top electrode including a lower top electrode portion on the lower dielectric layer in the trench and an upper top electrode portion on the upper dielectric layer outside the trench.

6. The semiconductor device of claim 3 , wherein the isolation layer is on a bottom of the trench and the lower dielectric layer is on an upper surface of the isolation layer at the bottom of the trench, and the lower conductive layer comprises a terminal portion that contacts the upper surface of the isolation layer at the bottom of the trench.

7. The semiconductor device of claim 1 , wherein the vertical channel is on a sidewall of the trench, and the transistor further comprises a gate dielectric between the vertical channel and the gate electrode in the trench.

8. The semiconductor device of claim 7 , wherein the vertical channel extends upward along the sidewall of the trench from the drain electrode to the source electrode.

9. A method of forming a semiconductor device, comprising:

forming a trench in an insulating base;

forming a transistor, wherein the transistor comprises a gate electrode and a vertical channel formed within the trench, and a drain electrode and a source electrode formed outside the trench;

forming an isolation layer on the gate electrode in the trench; and

forming a capacitor including a trench capacitor portion that is on the isolation layer in the trench, and a stacked capacitor portion that is coupled to the source electrode of the transistor outside the trench, wherein the forming of the capacitor comprises:

forming a lower conductive layer on the isolation layer in the trench; and

forming a plurality of stacked conductive layers outside the trench, the plurality of stacked conductive layers being coupled to the source electrode of the transistor.

10. The method of claim 9 , wherein the forming of the capacitor further comprises forming a lower dielectric layer on the lower conductive layer in the trench, and forming an upper dielectric layer on the plurality of stacked conductive layers.

11. The method of claim 10 , wherein the forming of the lower dielectric layer comprises forming the lower dielectric layer outside the trench and connected to the upper dielectric layer.

12. The method of claim 11 , wherein the forming of the capacitor further comprises forming a top electrode including a lower top electrode portion formed on the lower dielectric layer in the trench, and an upper top electrode portion formed on the upper dielectric layer outside the trench.

13. The method of claim 10 , wherein the forming of the isolation layer comprises forming the isolation layer on a bottom of the trench, and

wherein the forming of the lower dielectric layer comprises forming the lower dielectric layer on an upper surface of the isolation layer at the bottom of the trench, and the forming of the lower conductive layer comprises forming a terminal portion of the lower conductive layer that contacts the upper surface of the isolation layer at the bottom of the trench.

14. The method of claim 9 , wherein the forming of the isolation layer comprises forming the isolation layer on an upper surface of the gate electrode such that the isolation layer isolates the gate electrode from the stacked capacitor portion.

15. The method of claim 9 , wherein the forming of the transistor comprises forming the drain electrode in the insulating base outside the trench.

16. The method of claim 15 , wherein the forming of the transistor further comprises:

forming the vertical channel on a sidewall of the trench, the vertical channel extending upward along the sidewall of the trench from the drain electrode to the source electrode; and

forming a gate dielectric on the vertical channel in the trench.

17. A dynamic random access memory (DRAM) device comprising:

an insulating base including a trench;

a first memory cell comprising:

a first transistor formed within the trench; and

a first capacitor comprising:

a first trench capacitor portion including a first lower conductive layer formed within the trench;

a first stacked capacitor portion including a first plurality of stacked conductive layers formed outside the trench;

a second memory cell comprising:

a second transistor formed within the trench; and

a second capacitor comprising:

a second trench capacitor portion including a second lower conductive layer formed within the trench; and

a second stacked capacitor portion including a second plurality of stacked conductive layers formed outside the trench; and

an isolation layer formed within the trench and isolating the first memory cell from the second memory cell.

18. The DRAM device of claim 17 , further comprising:

a first bit line coupled to a first drain electrode of the first transistor in the first memory cell;

a second bit line coupled to a second drain electrode of the second transistor in the second memory cell; and

a word line coupled to a first gate electrode of the first transistor in the first memory cell, and a second gate electrode of the second transistor in the second memory cell.