Method for manufacturing semiconductor device
The present disclosure provides a method for manufacturing a semiconductor device having a buried wordline. The method includes forming a first recessed portion in a first dielectric layer in a substrate; forming a second recessed portion spaced apart from the first recessed portion and in the substrate; disposing a protection layer on the substrate to cover the second recessed portion; and disposing a second dielectric layer on the first dielectric layer.
1. A method of manufacturing a semiconductor device, comprising:
forming a first recessed portion in a first dielectric layer in a substrate;
forming a second recessed portion spaced apart from the first recessed portion and in the substrate;
disposing a protection layer on the substrate to cover the second recessed portion; and
disposing a second dielectric layer on the first dielectric layer.
2. The method of claim 1 , wherein the first recessed portion is deeper than the second recessed portion.
3. The method of claim 1 , wherein the first dielectric layer is disposed by a chemical vapor deposition (CVD) process.
4. The method of claim 1 , wherein the second dielectric layer is disposed by an atomic layer deposition (ALD) process.
5. The method of claim 1 , further comprising:
removing the protection layer to expose the second recessed portion; and
disposing a third dielectric layer in the second recessed portion.
6. The method of claim 5 , wherein the third dielectric layer is disposed by a thermal oxidation process.
7. The method of claim 5 , further comprising:
forming a first conductive layer on the second dielectric layer, wherein the first conductive layer is separated from the substrate by the first dielectric layer and the second dielectric layer.
8. The method of claim 7 , further comprising:
forming a second conductive layer on the third dielectric layer, wherein the second conductive layer is separated from the substrate by the third dielectric layer.
9. The method of claim 8 , wherein the first conductive layer and the second conductive layer comprises wordlines and are configured to address different memory cells.
10. The method of claim 8 , wherein the first dielectric layer comprises a first sublayer and a second sublayer disposed between the first sublayer and the first conductive layer.
11. The method of claim 10 , wherein a density of the second sublayer is different from a density of the first sublayer.
12. The method of claim 10 , wherein a density of the second sublayer is greater than a density of the first sublayer.
13. The method of claim 10 , wherein a density of the second dielectric layer is lower than a density of the second sublayer and higher than a density of the first sublayer.
14. The method of claim 10 , wherein a top surface of the first sublayer and a top surface of the second sublayer are substantially coplanar.
15. The method of claim 10 , wherein the first conductive layer comprises a passing wordline and the second conductive layer comprises an active wordline.
16. The method of claim 10 , wherein the first conductive layer and the second conductive layer are configured to receive different voltages.
17. The method of claim 1 , wherein a thickness of the first dielectric layer is greater than a thickness of the second dielectric layer.