Semiconductor memory device

1. A semiconductor memory device comprising:

a substrate including a plurality of block areas, each of the plurality of block areas being provided to extend in a first direction, and the plurality of block areas being arranged in a second direction that intersects the first direction;

a plurality of members, each of the plurality of members being provided to extend in the first direction, and being respectively disposed at a boundary portion between the plurality of block areas;

a plurality of conductive layers partitioned by the plurality of members, the plurality of conductive layers being arranged in a third direction that intersects the first direction and the second direction, and being disposed separately from each other; and

a plurality of pillars disposed in each of the plurality of block areas, each of the plurality of pillars being provided to penetrate the plurality of conductive layers, a portion at which one of the plurality of pillars and one of the plurality of conductive layers intersect functioning as a memory cell,

wherein at least one member of the plurality of members includes a plurality of first portions and a second portion, the plurality of first portions being arranged in the first direction, and the second portion being disposed between any two adjacent ones of the plurality of first portions,

when either one of one of the plurality of first portions and the second portion of the one member is referred to as a third portion, and the other one of the one of the plurality of first portions and the second portion of the one member is referred to as a fourth portion, the third portion has a width in the second direction greater than a width of the fourth portion in the second direction, and the third portion has a length in the first direction greater than the width of the fourth portion in the second direction,

the plurality of first portions of the member have a same layer structure as the second portion,

the fourth portion of the member includes a seam,

the third portion of the member includes a void,

the one member includes a contact and an insulating film, the contact including a portion provided to extend in the first direction, and the insulating film being provided between the contact and the plurality of conductive layers, and

the contact includes the seam.

2. The device of claim 1 , wherein

the one member has the plurality of second portions arranged at intervals in the first direction, and each of the plurality of first portions is disposed between any two adjacent ones of the plurality of second portions.

3. The device of claim 1 , wherein

the one member includes a bottom portion, a middle portion, and an upper portion arranged in the third direction from a side of the substrate, the middle portion of the member having a width greater than a width of the bottom portion and greater than a width of the upper portion in the second direction, and

the middle portion of the fourth portion of the one member includes the seam, and the middle portion of the third portion of the member includes the void.

4. The device of claim 1 , further comprising:

a plurality of bit lines each having a portion provided to extend in the second direction, each of the plurality of bit lines being coupled to at least one of the plurality of pillars in each of the plurality of block areas; and

a shunt line having a portion provided to extend in the second direction, the plurality of members including contacts respectively and the shunt line being coupled to at least one of the contacts included in the plurality of members,

wherein the substrate includes a memory area that includes the plurality of pillars, the memory area includes a shunt area that includes the shunt line and does not include the plurality of bit lines, and the shunt area includes the third portion of the one member.

5. The device of claim 1 , further comprising:

a plurality of bit lines each having a portion provided to extend in the second direction, and each of the plurality of bit lines being coupled to at least one of the plurality of pillars in each of the plurality of block areas; and

a shunt line having a portion provided to extend in the second direction, the plurality of members including contacts respectively and the shunt line being coupled to at least one of the contacts included in the plurality of members,

wherein the substrate includes a memory area that includes the plurality of pillars, the memory area includes a shunt area that includes the shunt line and does not include the plurality of bit lines, and the shunt area includes the fourth portion of the one member.

6. The device of claim 1 , wherein

the plurality of first portions of the member are disposed adjacent to the plurality of pillars in the second direction.

7. The device of claim 1 , wherein

the second portion of the member is disposed adjacent to the plurality of pillars in the second direction.

8. A semiconductor memory device comprising:

a substrate including a plurality of block areas, each of the plurality of block areas being provided to extend in a first direction, and the plurality of block areas being arranged in a second direction that intersects the first direction;

a plurality of members, each of the plurality of members being provided to extend in the first direction, and being respectively disposed at a boundary portion between the plurality of block areas;

a plurality of conductive layers partitioned by the plurality of members, the plurality of conductive layers being arranged in a third direction that intersects the first direction and the second direction, and being disposed separately from each other; and

a plurality of pillars disposed in each of the plurality of block areas, each of the plurality of pillars being provided to penetrate the plurality of conductive layers, a portion at which one of the plurality of pillars and one of the plurality of conductive layers intersect functioning as a memory cell,

wherein at least one member of the plurality of members includes a first portion and a second portion arranged in the first direction,

when either one of one of the first portion and the second portion of the one member is referred to as a third portion, and the other one of the one of the first portion and the second portion of the one member is referred to as a fourth portion, the third portion has a width in the second direction greater than a width of the fourth portion in the second direction,

the fourth portion of the one member includes a seam, and the third portion of the member includes a void,

the one member includes a contact and an insulating film, the contact including a portion provided to extend in the first direction, and the insulating film being provided between the contact and the plurality of conductive layers, and

the contact includes the seam.

9. The device of claim 8 , wherein

the one member includes a bottom portion, a middle portion, and an upper portion provided in the third direction from a side of the substrate, and the middle portion of the one member has a width greater than a width of the bottom portion and greater than a width of the upper portion in the second direction.

10. The device of claim 8 , wherein

the one member includes a plurality of first portions and the second portion; and

the one member has the plurality of first portions arranged in the first direction, and the second portion is disposed between any two adjacent ones of the plurality of first portions.

11. The device of claim 8 , wherein

the third portion has a length in the first direction greater than the width of the fourth portion in the second direction.

12. The device of claim 8 , wherein

the one member further includes seams arranged at intervals in the first direction.

13. The device of claim 12 , wherein

the one member includes a void between any two adjacent ones of the seams.

14. The device of claim 8 , further comprising:

a plurality of bit lines each having a portion provided to extend in the second direction, each of the plurality of bit lines being coupled to at least one of the plurality of pillars in each of the plurality of block areas; and

a shunt line having a portion provided to extend in the second direction, the plurality of members including contacts respectively and the shunt line being coupled to at least one of the contacts included in the plurality of members,

wherein the substrate includes a memory area that includes the plurality of pillars, the memory area includes a shunt area that includes the shunt line and does not include the plurality of bit lines, and the shunt area includes the third portion of the member.

15. The device of claim 8 , further comprising:

a plurality of bit lines each having a portion provided to extend in the second direction, each of the plurality of bit lines being coupled to at least one of the plurality of pillars in each of the plurality of block areas; and

a shunt line having a portion provided to extend in the second direction, the plurality of members including contacts respectively and the shunt line being coupled to at least one of the contacts included in the plurality of members,

wherein the substrate includes a memory area that includes the plurality of pillars, the memory area includes a shunt area that includes the shunt line and does not include the plurality of bit lines, and the shunt area includes the fourth portion of the member.