Variable resistance memory device

1. A variable resistance memory device, comprising:

a substrate;

memory cell structures on the substrate, the memory cell structures being spaced apart from each other in a first direction and a second direction, and the first direction and the second direction being parallel to a top surface of the substrate and intersecting each other; and

a dummy cell structure surrounding each of the memory cell structures, as viewed in a plan view, the dummy cell structure being a single body structure extending continuously between all the memory cell structures,

wherein each of the memory cell structures includes:

first conductive lines;

second conductive lines on the first conductive lines and intersecting the first conductive lines; and

memory cells between the first conductive lines and the second conductive lines, and

wherein the dummy cell structure includes:

first dummy conductive lines;

second dummy conductive lines on the first dummy conductive lines and intersecting the first dummy conductive lines; and

dummy memory cells between the first dummy conductive lines and the second dummy conductive lines.

2. The variable resistance memory device as claimed in claim 1 , wherein:

the first conductive lines extend in the first direction and are spaced apart from each other in the second direction, and

the first dummy conductive lines extend in the first direction and are spaced apart from each other in the second direction.

3. The variable resistance memory device as claimed in claim 2 , wherein each of the memory cell structures is between a pair of the first dummy conductive lines that are spaced apart from each other in the second direction.

4. The variable resistance memory device as claimed in claim 3 , wherein:

each of the first conductive lines has a first width in the second direction, and

each of the first dummy conductive lines has a second width in the second direction, the second width being equal to the first width.

5. The variable resistance memory device as claimed in claim 3 , wherein:

the second conductive lines extend in the second direction and are spaced apart from each other in the first direction, and

the second dummy conductive lines extend in the second direction and are spaced apart from each other in the first direction.

6. The variable resistance memory device as claimed in claim 5 , wherein each of the memory cell structures is between a pair of the second dummy conductive lines that are spaced apart from each other in the first direction.

7. The variable resistance memory device as claimed in claim 6 , wherein:

each of the second conductive lines has a third width in the first direction, and

each of the second dummy conductive lines has a fourth width in the first direction, the third width being equal to the fourth width.

8. The variable resistance memory device as claimed in claim 6 , wherein:

the substrate includes cell regions, on which the memory cell structures are positioned, and a core region between the cell regions,

the first conductive lines extend from each of the cell regions onto the core region in the first direction, and

ends of the first conductive lines are aligned with each other in the second direction on the core region.

9. The variable resistance memory device as claimed in claim 8 , wherein:

the second conductive lines extend from each of the cell regions onto the core region in the second direction, and

ends of the second conductive lines are aligned with each other in the first direction on the core region.

10. The variable resistance memory device as claimed in claim 9 , wherein:

the second conductive lines intersect some of the first dummy conductive lines, and

some of the second dummy conductive lines intersect the first conductive lines.

11. The variable resistance memory device as claimed in claim 10 , wherein the dummy memory cells are at intersection points of the second dummy conductive lines and the first dummy conductive lines, intersection points of the second dummy conductive lines and the first conductive lines, and intersection points of the second conductive lines and the first dummy conductive lines, respectively.

12. The variable resistance memory device as claimed in claim 6 , wherein:

the substrate includes cell regions, on which the memory cell structures are positioned, and a core region between the cell regions,

ends of the first conductive lines are aligned with each other in the second direction on each of the cell regions, and

ends of the second conductive lines are aligned with each other in the first direction on each of the cell regions.

13. The variable resistance memory device as claimed in claim 1 , wherein:

the substrate includes cell regions, on which the memory cell structures are positioned, and a core region between the cell regions, and

the dummy cell structure is on the core region and is in the single body structure that extends continuously along the core region.

14. The variable resistance memory device as claimed in claim 13 , wherein:

the core region includes a contact region on which conductive contacts are positioned, and

the dummy cell structure extends along the core region except the contact region.

15. The variable resistance memory device as claimed in claim 14 , further comprising a peripheral circuit structure on the substrate,

wherein the memory cell structures, the dummy cell structure, and the conductive contacts are on the peripheral circuit structure, and

wherein the conductive contacts are electrically connected to peripheral transistors of the peripheral circuit structure.

16. The variable resistance memory device as claimed in claim 1 , wherein each of the memory cells and the dummy memory cells includes a variable resistance pattern and a switching pattern, which are stacked in a third direction perpendicular to the top surface of the substrate.

17. A variable resistance memory device, comprising:

a substrate;

memory cell structures spaced apart from each other in a first direction and a second direction on the substrate, the first and second directions being parallel to a top surface of the substrate and intersecting each other; and

a single dummy cell structure between the memory cell structures,

wherein the single dummy cell structure extends between adjacent ones of the memory cell structures that are spaced apart from each other in the first direction, and between adjacent ones of the memory cell structures that are spaced apart from each other in the second direction,

wherein each of the memory cell structures includes:

first conductive lines;

second conductive lines on and intersecting the first conductive lines; and

memory cells between the first conductive lines and the second conductive lines, and

wherein the single dummy cell structure includes:

first dummy conductive lines;

second dummy conductive lines on and intersecting the first dummy conductive lines; and

dummy memory cells between the first dummy conductive lines and the second dummy conductive lines.

18. The variable resistance memory device as claimed in claim 17 , wherein the single dummy cell structure surrounds each of the memory cell structures when viewed in a plan view.

19. The variable resistance memory device as claimed in claim 17 , wherein:

the first dummy conductive lines include a same material as the first conductive lines, and

the second dummy conductive lines include a same material as the second conductive lines.

20. The variable resistance memory device as claimed in claim 17 , wherein each of the memory cells and the dummy memory cells includes a variable resistance pattern and a switching pattern, which are stacked in a third direction perpendicular to the top surface of the substrate.