Basic logic element, semiconductor device including the same, output control method for basic logic element, and non-transitory computer readable medium
A basic logic element includes: a calculation unit configured to perform calculation processing; a self-diagnosis unit configured to self-diagnose whether or not there is an abnormality in a result of the calculation output from the basic logic element; a management unit configured to determine whether or not to retain authority to output the result of the calculation based on a result of the diagnosis performed by the self-diagnosis unit and output a result of the determination as an authority signal; and an output control unit configured to control whether or not to output the result of the calculation performed by the calculation unit based on whether or not the authority to output data is retained by the management unit.
1. A basic logic element comprising:
one or more processors; and
a memory storing instructions executable by the one or more processors to:
perform calculation processing on an input signal, yielding a calculation result;
self-diagnose whether or not there is an abnormality in the calculation result;
retain or relinquish authority to output the calculation result based on whether or not the abnormality has been self-diagnosed in the calculation result;
in response to the authority having been retained, output the calculation result; and
in response to the authority having been relinquished, not output the calculation result.
2. The basic logic element according to claim 1 , wherein
the authority to output the calculation result is retained when no abnormality has been self-diagnosed in the calculation result, and
the authority to output the calculation result is relinquished when the abnormality has been self-diagnosed in the calculation result.
3. The basic logic element according to claim 1 , wherein the instructions are executable by the one or more processors to further:
retain the authority to output the calculation result in response to receiving an authority signal indicating that a different base logic element has relinquished the authority to output the calculation result.
4. The basic logic element according to claim 1 , wherein whether or not there is the abnormality in the calculation result is self-diagnosed by comparing first self-diagnosis data obtained from the calculation result with second self-diagnosis data received from each of at least one different basic logic element.
5. The basic logic element according to claim 4 , wherein whether or not there is the abnormality in the calculation result is self-diagnoses based on whether or not the first self-diagnosis indicates a value indicated by a majority of the first self-diagnosis data and the second self-diagnosis data output from each of the at least one different basic logic element.
6. The basic logic element according to claim 4 , wherein the instructions are executable by the one or more processors to further:
in response to having self-diagnosed the abnormality in the calculation result, output the second self-diagnosis data received from each the at least one different basic logic element.
7. The basic logic element according to claim 1 , wherein the basic logic element is used for at least one of a plurality of basic logic elements provided on a Field Programmable Gate Array (FPGA).
8. The basic logic element according to claim 1 , wherein the basic logic element is used for at least one of a plurality of basic logic elements provided in a dynamic reconfigurable processor.
9. A semiconductor device comprising a plurality of basic logic elements provided in parallel, each of the plurality of basic logic elements comprising:
one or more processors; and
a memory storing instructions executable by the one or more processors to:
perform calculation processing on an input signal, yielding a calculation result;
self-diagnose whether or not there is an abnormality in the calculation result;
retain or relinquish authority to output the calculation result of the calculation based on whether or not the abnormality has been self-diagnosed in the calculation result;
in response to the authority having been retained, output the calculation result; and
in response to the authority having been relinquished, not output the calculation result.
10. The semiconductor device according to claim 9 , wherein
in each of the plurality of basic logic elements,
the authority to output the calculation result is retained when no abnormality has been self-diagnosed in the calculation result, and
the authority to output the calculation result is relinquished when the abnormality the has been self-diagnosed in the calculation result.
11. The semiconductor device according to claim 9 , wherein in each of the plurality of basic logic elements, the instructions are executable by the one or more processors to further:
retain the authority to output the calculation result in response to receiving an authority signal indicating that a different base logic element has relinquished the authority to output the calculation result.
12. The semiconductor device according to claim 9 , wherein in each of the plurality of basic logic elements, whether or not there is the abnormality in the calculation result is self-diagnosed by comparing first self-diagnosis data obtained from the calculation result with second self-diagnosis data received from each of at least one different basic logic element.
13. The semiconductor device according to claim 12 , wherein in each of the plurality of basic logic elements, whether or not there is the abnormality in the calculation result is self-diagnoses based on whether or not the first self-diagnosis indicates a value indicated by a majority of the first self-diagnosis data and the second self-diagnosis data output from each of the at least one different basic logic element.
14. The semiconductor device according to claim 12 , wherein in each of the plurality of basic logic elements, wherein the instructions are executable by the one or more processors to further:
in response to having self-diagnosed the abnormality in the calculation result, output the second self-diagnosis data received from each the at least one different basic logic element.
15. The semiconductor device according to claim 9 , wherein the plurality of basic logic elements are part of a plurality of basic logic elements provided on a Field Programmable Gate Array (FPGA).
16. The semiconductor device according to claim 9 , wherein the plurality of basic logic elements are part of a plurality of basic logic elements provided in a dynamic reconfigurable processor.
17. An output control method executable by a basic logic element, the output control method comprising:
performing calculation processing on an input signal, yielding a calculation result;
self-diagnosing whether or not there is an abnormality in the calculation result;
retaining or relinquishing authority to output the result of the calculation result based on whether or not the abnormality has been self-diagnosed in the calculation result;
in response to the authority having been retained, outputting the calculation result; and
in response to the authority having been relinquished, not outputting the calculation result.
18. A non-transitory computer readable medium storing a control program executable by a basic logic element to perform processing comprising:
performing calculation processing on an input signal, yielding a calculation result;
self-diagnosing whether or not there is an abnormality in the calculation result;
retaining or relinquishing authority to output the result of the calculation result based on whether or not the abnormality has been self-diagnosed in the calculation result;
in response to the authority having been retained, outputting the calculation result; and
in response to the authority having been relinquished, not outputting the calculation result.