IP Library › Granted Patent US 11,900,161
Granted Patent B2
US 11,900,161 · App. 16/828,190 · Granted Feb 13, 2024

Memory allocation for processing-in-memory operations

Inventors: Anirban Nag (Milpitas, CA); Nuwan Jayasena (Santa Clara, CA); Shaizeen Aga (Santa Clara, CA)
Assignee: ADVANCED MICRO DEVICES, INC.
G06F9/5016G06F9/546G06F12/0246G06F12/0882G06F12/1027G06F2212/657
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Quick Facts
Patent No.
US 11,900,161
App. No.
16/828,190
Granted
Feb 13, 2024
Kind
B2
Abstract

Memory allocation for processing-in-memory operations, including: receiving, by an allocation module, a memory allocation request indicating a plurality of data structure operands for a processing-in-memory operation; determining a memory allocation pattern for the plurality of data structure operands, wherein the memory allocation pattern interleaves a plurality of component pages of a memory page across the plurality of data structure operands; and allocating the memory page based on the determined memory allocation pattern.

Claims (38)

1. A method of memory allocation for processing-in-memory operations, the method comprising:

receiving a memory allocation request indicating a plurality of data structure operands for a processing-in-memory operation; and

allocating a memory page based on a memory allocation pattern for the plurality of data structure operands, wherein the memory allocation pattern is determined by a compiler and indicated by a parameter in the received memory allocation request.

2. The method of claim 1 , wherein allocating the memory page comprises allocating component pages corresponding to different data structure operands within a same row of a memory array.

3. The method of claim 1 , wherein allocating the memory page comprises allocating component pages for each data structure operand to different banks of a memory module.

4. The method of claim 1 , further comprising:

identifying, by the compiler, for the plurality of data structure operands, an identifier corresponding to the processing-in-memory operation; and

generating, by the compiler, an executable code command that, when executed, causes generation of the memory allocation request.

5. The method of claim 4 , wherein the executable code command indicates the memory allocation pattern.

6. The method of claim 4 , wherein the identifier is included in a plurality of identifiers each corresponding to a respective processing-in-memory operation, and the method further comprises:

determining, by the compiler, based on the plurality of identifiers, a plurality of data structure operand groupings, wherein generating the executable code command comprises generating, for each data structure operand grouping of the plurality of data structure operand groupings, a corresponding executable code command.

7. The method of claim 1 , further comprising storing, in a processing-in-memory translation lookaside buffer, one or more entries each facilitating translation between an application-level virtual address to a virtual address of a component page.

8. An apparatus for memory allocation for processing-in-memory operations, the apparatus comprising:

a processor; and

a memory coupled to the processor, wherein the memory comprises instructions executed by the processor to:

receive a memory allocation request indicating a plurality of data structure operands for a processing-in-memory operation; and

allocate a memory page based on a memory allocation pattern for the plurality of data structure operands, wherein the memory allocation pattern is determined by a compiler and indicated by a parameter in the received memory allocation request.

9. The apparatus of claim 8 , wherein allocating the memory page comprises allocating component pages corresponding to different data structure operands within a same row of a memory array.

10. The apparatus of claim 8 , wherein allocating component pages for each data structure operand to different banks of a memory module.

11. The apparatus of claim 8 , wherein the processor is further configured to execute instructions to:

identify, by the compiler, for the plurality of data structure operands, an identifier corresponding to the processing-in-memory operation; and

generate, by the compiler, an executable code command that, when executed, causes generation of the memory allocation request.

12. The apparatus of claim 11 , wherein the processor is further configured to execute instructions to:

determine, by the compiler, the memory allocation pattern, wherein the executable code command indicates the memory allocation pattern.

13. The apparatus of claim 11 , wherein the identifier is included in a plurality of identifiers each corresponding to a respective processing-in-memory operation, and the processor is further configured to execute instructions to determine, by the compiler, based on the plurality of identifiers, a plurality of data structure operand groupings, wherein generate the executable code command comprises generating, for each data structure operand grouping of the plurality of data structure operand groupings, a corresponding executable code command.

14. The apparatus of claim 8 , wherein the processor is further configured to execute instructions to store in a processing-in-memory translation lookaside buffer, one or more entries each facilitating translation between an application-level virtual address to a virtual address of a component page.

15. A computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a processor to:

receive a memory allocation request indicating a plurality of data structure operands for a processing-in-memory operation; and

allocate a memory page based on a memory allocation pattern for the plurality of data structure operands, wherein the memory allocation pattern is determined by a compiler and indicated by a parameter in the received memory allocation request.

16. The computer program product of claim 15 , wherein allocating the memory page further comprises allocating component pages corresponding to different data structure operands within a same row of a memory array.

17. The computer program product of claim 15 , wherein allocating the memory page further comprises allocating pages for each data structure operand to different banks of a memory module.

18. The computer program product of claim 15 , further comprising instructions that, when executed, cause the processor to:

identify, by the compiler, for the plurality of data structure operands, an identifier corresponding to the processing-in-memory operation; and

generate, by the compiler, an executable code command that, when executed, causes generation of the memory allocation request.

19. The computer program product of claim 18 , further comprising instructions that, when executed, cause the processor to:

determine, by the compiler, the memory allocation pattern, wherein the executable code command indicates the memory allocation pattern.

20. The computer program product of claim 18 , wherein the identifier is included in a plurality of identifiers each corresponding to a respective processing-in-memory operation, and further comprising instructions that, when executed, cause the processor to:

determine, by the compiler, based on the plurality of identifiers, a plurality of data structure operand groupings, wherein the instructions for processing-in-memory operations that, when executed, cause the processor to generate the executable code command comprises instructions for processing-in-memory operations that, when executed, cause the processor to generate, for each data structure operand grouping of the plurality of data structure operand groupings, a corresponding executable code command.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2020
From: NAG, ANIRBAN; JAYASENA, NUWAN; AGA, SHAIZEEN
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 052211/0165 →
Continuity (1)
Related Publication 20210303355A1 · Sep 30, 2021