Semiconductor package including a fillet layer

1. A semiconductor package, comprising:

a base substrate including a first semiconductor substrate and a first protective layer at least partially covering a top surface of the first semiconductor substrate;

a first semiconductor chip disposed on the first protective layer;

a first fillet layer at least partially filling a space between the first protective layer and the first semiconductor chip; and

a molding contacting the base substrate and enclosing the first semiconductor chip and the first fillet layer, wherein the first semiconductor chip and the first fillet layer are disposed between the molding and the base substrate in a direction perpendicular to an upper surface of the first semiconductor substrate,

wherein the first protective layer includes a first trench extending partially through a thickness of the first protective layer and totally overlapping the first semiconductor chip such that a bottom surface of the first protective layer and the top surface of the first semiconductor substrate are planar, and

wherein a part of the first fillet layer directly contacts the first protective layer and at least partially fills the first trench.

2. The semiconductor package of claim 1 , wherein the first semiconductor chip includes a second semiconductor substrate, and a semiconductor element layer disposed between the second semiconductor substrate and the first fillet layer.

3. The semiconductor package of claim 1 , further comprising:

a second semiconductor chip disposed on the first semiconductor chip; and

a second fillet layer at least partially filling a space between the first semiconductor chip and the second semiconductor chip.

4. The semiconductor package of claim 3 , wherein the first semiconductor chip includes a second semiconductor substrate, and a second protective layer at least partially covering a top side of the second semiconductor substrate,

wherein the second protective layer includes a second trench extending partially through a thickness of the second protective layer and totally overlapping the second semiconductor chip such that a bottom surface of the second protective layer and a top surface of the second semiconductor substrate are planar, and

wherein a part of the second fillet layer at least partially fills the second trench.

5. The semiconductor package of claim 1 , wherein the base substrate includes a side surface extending primarily in a first direction, and

wherein a long side of the first trench extends primarily in the first direction.

6. The semiconductor package of claim 5 , wherein the first trench includes a first sub-side trench and a second sub-side trench, spaced apart from each other.

7. The semiconductor package of claim 6 , wherein the first sub-side trench is closer to the side surface of the base substrate than it is to the second sub-side trench.

8. The semiconductor package of claim 7 , wherein a length of the first sub-side trench in the first direction is longer than a length of the second sub-side trench in the first direction.

9. The semiconductor package of claim 1 , wherein the first trench for s a concave surface facing away from a center of the base substrate.

10. The semiconductor package of claim 1 , wherein an entirety of a bottom surface of sidewalls of the molding make contact with a top surface of the base substrate.

11. A semiconductor package, comprising:

a base substrate including a first semiconductor substrate and a first protective layer at least partially covering a top surface of the first semiconductor substrate;

a first semiconductor chip disposed on the first protective layer;

a first fillet layer at least partially filling a space between the first protective layer and the first semiconductor chip; and

a molding contacting the base substrate and enclosing the first semiconductor chip and the first fillet layer, wherein the first semiconductor chip and the first fillet layer are disposed between the molding and the base substrate in a direction perpendicular to an upper surface of the first semiconductor substrate,

wherein the first protective layer includes a first trench recessed from a top surface of the first protective layer and totally overlapping the first semiconductor chip such that a bottom surface of the first protective layer extends along the top surface of the first semiconductor substrate,

wherein the bottom surface of the first protective layer is planar over its entirety; and

wherein a part of the first fillet layer directly contacts the first protective layer and at least partially fills the first trench.

12. The semiconductor package of claim 11 , wherein an entirety of a bottom surface of sidewalls of the molding make contact with a top surface of the base substrate.

13. The semiconductor package of claim 11 , wherein the first semiconductor chip includes a second semiconductor substrate, and a semiconductor element layer disposed between the second semiconductor substrate and the first fillet layer.

14. The semiconductor package of claim 11 , further comprising:

a second semiconductor chip disposed on the first semiconductor chip; and

a second fillet layer at least partially filling a space between the first semiconductor chip and the second semiconductor chip.

15. The semiconductor package of claim 14 , wherein the first semiconductor chip includes a second semiconductor substrate, and a second protective layer at least partially covering a top side of the second semiconductor substrate,

wherein the second protective layer includes a second trench recessed from a top surface of the second protective layer and totally overlapping the second semiconductor chip such that a bottom surface of the second protective layer extends along a top surface of the second semiconductor substrate, and

wherein a part of the second fillet layer at least partially fills the second trench.

16. The semiconductor package of claim 11 , wherein the base substrate includes a side surface extending primarily in first direction, and

wherein a long side of the first trench extends primarily in the first direction.

17. The semiconductor package of claim 10 , further comprising:

a penetration via penetrating both the first semiconductor substrate and the first protective layer; and

a bump electrically connecting the first penetration via and the first semiconductor chip.

18. The semiconductor package of claim 17 , further comprising:

a first connection pad connected to the penetration via, on the top surface of the first protective layer; and

a second connection pad disposed on a bottom surface of the first semiconductor chip,

wherein the bump connects the first connection pad to the second connection pad.

19. The semiconductor package of claim 18 , wherein the first semiconductor chip includes a second semiconductor substrate, and a semiconductor element layer disposed between the second semiconductor substrate and the first fillet layer, and

wherein the second connection pad connects the semiconductor element layer to the hump.