Series connected stacked vertical transistors for high voltage applications
A method of forming an electrical device that includes forming a multilayered fin composed of a first source/drain layer for a first transistor, a first channel layer for the first transistor, a common source/drain layer for the first transistor and a second transistor, a second channel layer for the second transistor and a second source/drain layer for the second transistor. A common spacer is formed on the common source/drain layer that separates a first opening to the first channel layer from a second opening to the second channel layer. Gate structures are then formed in the first and second openings.
1. An electrical device comprising:
a first vertical field effect transistor (VFET) including a first source/drain region present on a supporting substrate, a first channel region in direct contact with the first source/drain region and a common source/drain region;
a second vertical field effect transistor including the common source/drain region, a second channel region present on the common/source drain region, and a second source/drain region present on the second channel region, wherein the first and second vertical field effect transistors (VFETs) are vertically stacked upon one another the first channel region, the common source/drain region, the second channel region and the second source/drain region present within a fin structure, the first and second vertical field effect transistors being connected by the common source/drain region; and
a gate contact is in direct contact with each of a first gate structure to the first channel region of the first vertical field effect transistor and a second gate structure to the second channel region of the second vertical field effect transistor.
2. The electrical device of claim 1 , wherein the first source/drain region is a layer atop the supporting substrate having a greater width than the fin structure.
3. The electrical device of claim 1 , wherein the first vertical field effect transistor and the second vertical field effect transistor are connected in series across the common source/drain region.
4. The electrical device of claim 1 , wherein a drain contact is in direct contact with the second source/drain region, a source contacts is in direct contact with the first source/drain region.
5. The electrical device of claim 1 , wherein each of the first source/drain region, the common source/drain region and the second source/drain region have a same conductivity type.
6. The electrical device of claim 1 , wherein a first gate structure is present on the first channel region, and the first gate structure has a gate all around (GAA) structure.
7. The electrical device of claim 1 , wherein a second gate structure is present on the second channel region, and the second gate structures has a gate all around (GAA) structure.
8. The electrical device of claim 1 , wherein a first channel sidewall for the first channel region is aligned with a second channel sidewall for the second channel region.
9. An electrical device comprising:
a first vertical field effect transistor (VFET) including a first source/drain region present on a supporting substrate, a first channel region in direct contact with the first source/drain region and a common source/drain region;
a second vertical field effect transistor including the common source/drain region, a second channel region present on the common/source drain region, and a second source/drain region present on the second channel region, wherein the first and second vertical field effect transistors (VFETs) are vertically stacked upon one another the first channel region, the common source/drain region, the second channel region and the second source/drain region present within a fin structure, wherein the first and second vertical field effect transistors are connected by the common source/drain region; and
a metal semiconductor alloy present on a sidewall of the common source/drain region wherein the metal semiconductor alloy provides an electrical path between the first and second vertical field effect transistors having a resistance lower than a pathway directly through the common source/drain region without the metal semiconductor alloy.
10. The electrical device of claim 9 , wherein the first source/drain region is a layer atop the supporting substrate having a greater width than the fin structure.
11. The electrical device of claim 9 , wherein the first vertical field effect transistor and the second vertical field effect transistor are connected in series across the common source/drain region.
12. The electrical device of claim 9 , wherein a drain contact is in direct contact with the second source/drain region, a source contacts is in direct contact with the first source/drain region, and a gate contact is in direct contact with each of a first gate structure to the first channel region of the first vertical field effect transistor and a second gate structure to the second channel region of the second vertical field effect transistor.
13. The electrical device of claim 9 , wherein each of the first source/drain region, the common source/drain region and the second source/drain region have a same conductivity type.
14. The electrical device of claim 9 , wherein a first gate structure is present on the first channel region, and the first gate structure has a gate all around (GAA) structure.
15. The electrical device of claim 9 , wherein a second gate structure is present on the second channel region, and the second gate structures has a gate all around (GAA) structure.
16. The electrical device of claim 9 , wherein a first channel sidewall for the first channel region is aligned with a second channel sidewall for the second channel region.
17. An electrical device comprising:
a first semiconductor device including a first source/drain region present on a supporting substrate, a first channel region in direct contact with the first source/drain region and a common source/drain region;
a second semiconductor device including the common source/drain region, a second channel region present on the common/source drain region, and a second source/drain region present on the second channel region, wherein the first and second semiconductor devices are vertically stacked upon one another the first channel region, the common source/drain region, the second channel region and the second source/drain region present within a fin structure, the first and second vertical field effect transistors being connected by the common source/drain region to provide that the first semiconductor device and the second semiconductor device are connected in series; and
a gate contact in direct contact with each of a first gate structure to the first channel region of the first semiconductor device and a second gate structure to the second channel region of the second semiconductor device.
18. The electrical device of claim 17 , wherein a drain contact is in direct contact with the second source/drain region, a source contacts is in direct contact with the first source/drain region.
19. The electrical device of claim 17 , wherein each of the first source/drain region, the common source/drain region and the second source/drain region have a same conductivity type.