IP Library › Granted Patent US 11,903,128
Granted Patent B2
US 11,903,128 · App. 17/936,000 · Granted Feb 13, 2024

Wiring substrate

Inventor: Shigeto Iyoda (Ogaki, JP)
Assignee: IBIDEN CO., LTD.
H05K1/112H05K2201/09481H05K2201/09609
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Quick Facts
Patent No.
US 11,903,128
App. No.
17/936,000
Granted
Feb 13, 2024
Kind
B2
Abstract

A wiring substrate includes an insulating layer, a conductor layer formed on a surface of the insulating layer such that the conductor layer includes a conductor pad, and a solder resist layer formed on the surface of the insulating layer such that the solder resist layer is covering the conductor layer and having an opening exposing the conductor pad. The conductor pad of the conductor layer has a substantially rectangular planar shape such that the conductor pads has a main surface, a pair of long sides, a pair of short sides and four corner portions, and the solder resist layer is formed such that the opening is exposing side surfaces at the long sides and 50% or more of the main surface and that the solder resist layer is covering side surfaces at the short sides.

Claims (33)

1. A wiring substrate, comprising:

an insulating layer;

a conductor layer formed on a surface of the insulating layer such that the conductor layer includes a conductor pad; and

a solder resist layer formed on the surface of the insulating layer such that the solder resist layer is covering the conductor layer and having an opening exposing the conductor pad,

wherein the conductor pad of the conductor layer has a substantially rectangular planar shape such that the conductor pads has a main surface, a pair of long sides, a pair of short sides and four corner portions, and the solder resist layer is formed such that the opening is exposing side surfaces at the long sides and 50% or more of the main surface and that the solder resist layer is covering side surfaces at the short sides.

2. The wiring substrate according to claim 1 , wherein the conductor layer is formed such that the conductor pad is an independent pad that is not directly connected to another pad or a wiring formed in the conductor layer.

3. The wiring substrate according to claim 2 , further comprising:

a second conductor layer formed on a second surface of the insulating layer on an opposite side with respect to the conductor layer; and

a via conductor formed in the insulating layer such that the via conductor is connecting the second conductor layer and the conductor pad of the conductor layer such that the conductor pad forms a via pad.

4. The wiring substrate according to claim 2 , wherein the conductor layer is formed such that a distance between the pair of short sides of the conductor pad is in a range of 1.3 to 2.0 times a distance between the pair of long sides of the conductor pad.

5. The wiring substrate according to claim 2 , wherein the solder resist layer is formed such that the opening has a substantially rectangular planar shape.

6. The wiring substrate according to claim 2 , wherein the solder resist layer is formed such that the solder resist layer is covering the four corner portions of the conductor pad.

7. The wiring substrate according to claim 2 , further comprising:

a surface treatment layer covering the conductor pad.

8. The wiring substrate according to claim 2 , wherein the conductor layer is formed on a surface side of the wiring substrate on an opposite side with respect to a component mounting surface configured to mount a component.

9. The wiring substrate according to claim 8 , further comprising:

a plurality of component mounting pads forming the component mounting surface such that the conductor pad of the conductor layer is larger than each of the component mounting pads.

10. The wiring substrate according to claim 2 , wherein the conductor layer is formed such that the conductor pad is a connection pad configured to connect an external element.

11. The wiring substrate according to claim 1 , further comprising:

a second conductor layer formed on a second surface of the insulating layer on an opposite side with respect to the conductor layer; and

a via conductor formed in the insulating layer such that the via conductor is connecting the second conductor layer and the conductor pad of the conductor layer such that the conductor pad forms a via pad.

12. The wiring substrate according to claim 1 , wherein the conductor layer is formed such that a distance between the pair of short sides of the conductor pad is in a range of 1.3 to 2.0 times a distance between the pair of long sides of the conductor pad.

13. The wiring substrate according to claim 1 , wherein the solder resist layer is formed such that the opening has a substantially rectangular planar shape.

14. The wiring substrate according to claim 1 , wherein the solder resist layer is formed such that the solder resist layer is covering the four corner portions of the conductor pad.

15. The wiring substrate according to claim 1 , further comprising:

a surface treatment layer covering the conductor pad.

16. The wiring substrate according to claim 1 , wherein the conductor layer is formed on a surface side of the wiring substrate on an opposite side with respect to a component mounting surface configured to mount a component.

17. The wiring substrate according to claim 1 , wherein the conductor layer is formed such that the conductor pad is a connection pad configured to connect an external element.

18. The wiring substrate according to claim 16 , further comprising:

a plurality of component mounting pads forming the component mounting surface such that the conductor pad of the conductor layer is larger than each of the component mounting pads.

19. The wiring substrate according to claim 18 , further comprising:

a second solder resist layer covering peripheral edges of the component mounting pads and having a plurality of openings exposing portions of the component mounting pads other than the peripheral edges of the component mounting pads.

20. The wiring substrate according to claim 1 , wherein the conductor layer is formed such that each of the corner portions of the conductor pad is R-chamfered.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 28, 2022
From: IYODA, SHIGETO
To: IBIDEN CO., LTD.
Reel/Frame 061242/0364 →
Priority Claims (1)
JP 2021-165625 · Oct 7, 2021 · national
Continuity (1)
Related Publication 20230115650A1 · Apr 13, 2023