Vertical memory device
Disclosed is a vertically stacked 3D memory device, and the memory device may include a bit line extended vertically from a substrate, and including a first vertical portion and a second vertical portion, a vertical active layer configured to surround the first and second vertical portions of the bit line, a word line configured to surround the vertical active layer and the first vertical portion of the bit line, and a capacitor spaced apart vertically from the word line, and configured to surround the vertical active layer and the second vertical portion of the bit line.
1. A method for fabricating a memory device, comprising:
forming a bit line extending vertically from a peripheral circuit portion;
forming a capacitor surrounding the bit line;
forming a transistor including a vertical active layer extending vertically from a first side of the capacitor and a word line surrounding the vertical active layer; and
forming a plate line coupled to a second side of the capacitor, and extending vertically from the peripheral circuit portion,
wherein the forming of the transistor comprises:
forming a first source/drain layer coupled to the first side of the capacitor;
forming a vertical channel layer epitaxial-grown vertically from the first source/drain layer; and
forming a second source/drain layer epitaxial-grown horizontally from the vertical channel layer, and coupled to the bit line.
2. The method of claim 1 , wherein the first source/drain layer is formed of polysilicon doped with an impurity.
3. The method of claim 1 , wherein the forming of the second source/drain layer comprises forming an epitaxial silicon layer epitaxial-grown horizontally from the vertical channel layer, and
wherein the epitaxial silicon layer is doped with an impurity.
4. The method of claim 1 , wherein the forming of the capacitor comprises:
forming a multi-layer stack in which a first material, a second material and a third material are alternately stacked over the peripheral circuit portion;
forming an opening oriented vertically from the peripheral circuit portion by etching the multi-layer stack;
forming a capacitor recess by recessing the second material of the multi-layer stack; and
forming the capacitor including a plate node, a dielectric layer and a storage node in the capacitor recess.
5. The method of claim 4 , wherein the forming of the transistor further comprises:
forming a gate recess by recessing the first material of the multi-layer stack;
forming a gate dielectric layer in the gate recess; and
filling the word line that fills the gate recess, on the gate dielectric layer.
6. The method of claim 4 , wherein the forming of the plate line comprises:
forming a plate recess by removing all of the second material of the multi-layer stack to expose the second side of the capacitor;
forming a silicon line coupled to the second side of the capacitor, and filling the plate recess; and
forming a metal line coupled to the silicon line, and extending vertically from the peripheral circuit portion.
7. The method of claim 1 , further comprising forming an isolation layer between the plate line and the word line.
8. The method of claim 1 , further comprising forming a protective layer between the capacitor and the word line,
wherein the protective layer is extended to be located between the capacitor and the bit line.
9. The method of claim 1 , wherein the capacitor and the word line are alternately stacked on each other along an extension direction of the bit line.
10. The method of claim 1 , wherein the forming of the second source/drain layer comprises:
forming an epitaxial silicon layer epitaxial-grown horizontally from the vertical channel layer;
forming a sacrificial doped layer containing an impurity on the epitaxial silicon layer;
performing a heat treatment process to diffuse the impurity from the sacrificial doped layer; and
removing the sacrificial doped layer.
11. The method of claim 1 , further comprising forming a metal silicide layer on a surface of the second source/drain layer after the forming of the second source/drain layer.