IP Library › Granted Patent US 11,907,146
Granted Patent B2
US 11,907,146 · App. 17/987,703 · Granted Feb 20, 2024

Systems and methods for intelligently implementing concurrent transfers of data within a machine perception and dense algorithm integrated circuit

Inventors: Aman Sikka (Burlingame, CA); Marian Petre (Burlingame, CA); Nigel Drego (Burlingame, CA); Veerbhan Kheterpal (Burlingame, CA)
Assignee: quadric.io, Inc.
G06F13/28G06F2213/28
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Quick Facts
Patent No.
US 11,907,146
App. No.
17/987,703
Granted
Feb 20, 2024
Kind
B2
Abstract

System and method for implementing accelerated memory transfers in an integrated circuit includes identifying memory access parameters for configuring memory access instructions for accessing a target corpus of data from within a defined region of an n-dimensional memory; converting the memory access parameters to direct memory access (DMA) controller-executable instructions, wherein the converting includes: (i) defining dimensions of a data access tile based on a first parameter of the memory access parameters; (ii) generating multi-directional data accessing instructions that, when executed, automatically moves the data access tile along multiple distinct axes within the defined region of the n-dimensional memory based at least on a second parameter of the memory access parameters; transferring a corpus of data from the n-dimensional memory to a target memory based on executing the DMA controller-executable instructions.

Claims (68)

1. A method for accelerated memory transfers in an integrated circuit, the method comprising:

configuring a memory transfer of a target corpus of data from a double data rate (DDR) memory of the integrated circuit based on memory access parameters;

creating direct memory access (DMA) instructions for the memory transfer, wherein the creating the DMA instructions include:

(i) defining dimensions of a data access tile based on a first parameter of the memory access parameters;

(ii) generating multi-directional data accessing instructions that, when executed, automatically moves the data access tile along at least one axis of multiple distinct axes within the DDR memory based at least on a second parameter of the memory access parameters;

transferring the target corpus of data from the DDR memory to an array of processing cores of the integrated circuit based on executing the DMA instructions.

2. The method according to claim 1 , wherein creating the DMA instructions further includes:

(i) defining dimensions of a distinct data access tile for accessing data stored in an on-chip memory (OCM) based on the memory access parameters; and

(ii) generating multi-directional data accessing instructions that, when executed, automatically moves the distinct data access tile along at least one axis of multiple distinct axes within the OCM based on the memory access parameters.

3. The method according to claim 1 , wherein transferring the target corpus of data further includes:

transferring the target corpus of data from the DDR memory using the data access tile to an on-chip memory (OCM); and

transferring the target corpus of data from the OCM to the array of processing cores.

4. A method for accelerated memory transfers in an integrated circuit, the method comprising:

configuring a memory transfer of a target corpus of data from an on-chip memory (OCM) of the integrated circuit based on memory access parameters;

creating direct memory access (DMA) instructions for the memory transfer, wherein the creating the DMA instructions include:

(i) defining dimensions of a data access tile based on the memory access parameters;

(ii) generating multi-directional data accessing instructions that, when executed, automatically moves the data access tile along at least one axis of multiple distinct axes within the OCM based at least on the memory access parameters;

transferring the target corpus of data from the OCM to an array of processing circuits of the integrated circuit based on executing the DMA instructions.

5. The method according to claim 4 , further comprising:

generating intra-data access tile data accessing instructions that inform a pattern for collecting lines of data within a body of the data access tile, wherein the intra-data access tile data accessing instructions include:

a line-to-line movement instruction that informs a pattern of movement from an instant line of data within the data access tile at which an active collection of data is performed to a subsequent line of data within the body of the data access tile at which a subsequent collection of data will be performed, wherein the pattern of movement identifies a number of lines that are bypassed between the instant line of data and the subsequent line of data.

6. The method according to claim 5 , wherein

the intra-data access tile data accessing instructions further include:

a looping instruction that informs a number of instances of execution of the line-to-line movement instruction for collecting a plurality of distinct lines of data within the data access tile.

7. The method according to claim 4 , wherein

the multi-directional data accessing instructions include:

a tile transposition instruction that informs a pattern of moving the data access tile along a second direction of the OCM based on a completion of a collection of data by the data access tile along a first direction of the OCM.

8. The method according to claim 4 , wherein

the multi-directional data accessing instructions further include:

a tile transposition looping instruction that informs a number of instances of execution of a tile transposition instruction for collecting, by the data access tile, a plurality of distinct tiles of data within the OCM.

9. The method according to claim 4 , wherein executing the DMA instructions includes:

accessing data by moving the data access tile a predetermined number of times along a first direction within the OCM, and

upon completion of the movement of the data access tile along the first direction, (a) automatically moving the data access tile in a second direction within the OCM and (b) restarting the accessing data along the first direction within the OCM based on moving the data access tile in the second direction.

10. The method according to claim 9 , wherein

moving the data access tile in the second direction includes moving the data access tile to a location within the OCM that is nonoverlapping with a prior location within the OCM of the data access tile.

11. The method according to claim 4 , wherein

generating multi-directional data accessing instructions includes:

generating a sequence of base memory addresses, where each distinct base memory address of the sequence of base memory addresses is associated with a distinct iteration of the data access tile.

12. The method according to claim 4 , further comprising:

configuring a direct memory access (DMA) mask based on identifying that an iteration of the data access tile will likely exceed a boundary of the OCM, wherein the DMA mask includes data access instructions that, when executed, generate predetermined data values along an extent of the data access tile that exceeds the boundary of the OCM.

13. The method according to claim 4 , further comprising:

configuring exo-tile boundary data access instructions based on the memory access parameters requiring a collection of data that exceeds at least one boundary of the data access tile and encompasses the at least one boundary of the data access tile, wherein the exo-tile boundary data access instructions, when executed, causes a collection, by the data access tile, of data values encompassing the at least one boundary of the data access tile.

14. The method according to claim 4 , wherein

the memory access parameters include:

a first parameter of the memory access parameters that identifies dimensions of the OCM; and

a second parameter of the memory access parameters that identifies a data access scheme of a plurality of distinct data access schemes that informs a creation of the multi-directional data accessing instructions.

15. The method according to claim 14 , wherein

the memory access parameters further include:

a third parameter that identifies a second direction for performing data access using the data access tile within the OCM that is distinct from a first direction for data access using the data access tile within the OCM.

16. The method according to claim 4 , wherein

generating the multi-directional data accessing instructions includes generating transpositional DMA instructions that include:

(i) a data access pattern that, when executed, implements a plurality of distinct executions of a data collection tile at a plurality of distinct base memory addresses along the OCM, and

(ii) a transposition instruction that automatically moves the data collection tile from an instant base memory address to a subsequent base memory address of the plurality of distinct base memory addresses based on a completion of an accessing of data by the data access tile at the instant base memory address.

17. The method according to claim 4 , wherein

generating the multi-directional data accessing instructions includes generating recycling DMA instructions that include:

(i) a data access pattern that, when executed, implements an accessing of data by the data access tile at an instant base memory address of a sequence of base memory addresses within the OCM, and

(ii) a recycle instruction that, when executed, automatically recycles a data collection tile at a distinct base memory address of the sequence of base memory addresses based on a completion of the accessing of data by the data access tile at the instant base memory address.

18. A method comprising:

identifying, via a front-end application programming interface (API), a set of memory access parameters for transferring data between distinct memory components;

creating data fetching instructions executable by one or more circuits of an integrated circuit, wherein creating the data fetching instructions includes:

(i) defining a shape of a direct memory access (DMA) tile that, when executed, accesses data from within an on-chip memory (OCM);

(ii) generating multi-directional DMA instructions that, when executed, iterates the DMA tile along multiple distinct axes within the OCM for transferring a target corpus of data; and

transferring the target corpus of data from the OCM to a plurality of distinct processing cores of the integrated circuit based on executing the data fetching instructions.

19. The method according to claim 18 , further comprising:

implementing a front-end application programming interface (API) that receives the set of memory access parameters for transferring data between distinct memory components; and

implementing a DMA circuit that transfers the target corpus of data from the OCM to the plurality of distinct processing cores based on executing the data fetching instructions.

20. The method according to claim 18 , further comprising:

implementing an iterator application programming interface (API) executing a software development kit that converts the set of memory access parameters to the data fetching instructions executable by one or more circuits of the integrated circuit.

Assignments (2)
SECURITY INTEREST Recorded Apr 3, 2025
From: QUADRIC, INC.
To: DECATHLON ALPHA V, L.P.
Reel/Frame 070722/0441 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2022
From: SIKKA, AMAN; PETRE, MARIAN; DREGO, NIGEL; KHETERPAL, VEERBHAN
To: QUADRIC.IO, INC.
Reel/Frame 061790/0140 →
Continuity (3)
Continuation 17710353 · Mar 31, 2022
Provisional Application 63169673 · Apr 1, 2021
Related Publication 20230073276A1 · Mar 9, 2023