Computing system and method of verifying circuit design in computing system

1. A computing system configured to verify design of an integrated circuit, the computing system comprising:

a memory configured to store computer executable instructions; and

a processor configured to generate a first coverage model for at least two high-level parameters from the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard or hardware description language code by executing the computer executable instructions, generate a second coverage model for low-level internal signals from the hardware description language code by executing the computer executable instructions, and generate a plurality of test packets for a regression test by using at least one of the first coverage model or the second coverage model by executing the computer executable instructions.

2. The computing system of claim 1 , wherein the design of the integrated circuit comprises design of a receiver of a physical layer of a wireless local area network.

3. The computing system of claim 2 , wherein the first coverage model comprises a cross-coverage model in which the at least two high-level parameters are combined.

4. The computing system of claim 2 , wherein the at least two high-level parameters constitute a configuration of the physical layer of the wireless local area network, and

one of the at least two parameters comprises one of an encoding scheme, a modulation and coding scheme, a bandwidth, or a guard interval.

5. The computing system of claim 2 , wherein the second coverage model comprises a coverage model in which the low-level internal signals are sub-sampled.

6. The computing system of claim 5 , wherein the second coverage model uniformly sub-samples phase values of the low-level internal signals and geometrically sub-samples data or channel values of the low-level internal signals.

7. The computing system of claim 1 , wherein the processor is further configured to verify the design of the integrated circuit by using the plurality of test packets.

8. A computing system configured to verify design of a receiver of a physical layer according to the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard, the computing system comprising:

a memory configured to store computer executable instructions; and

a processor configured to generate a first coverage model for at least two high-level parameters from hardware description language code by executing the computer executable instructions, generate a second coverage model for low-level internal signals from the hardware description language code by executing the computer executable instructions, generate a plurality of test packets for a regression test by using at least one of the first coverage model or the second coverage model by executing the computer executable instructions, and verify the design of the receiver of the physical layer according to the plurality of test packets by executing the computer executable instructions.

9. The computing system of claim 8 , wherein the first coverage model comprises a cross-coverage model in which the at least two high-level parameters are combined.

10. The computing system of claim 8 , wherein the second coverage model comprises a sub-sampled coverage model for the low-level internal signals.