Low-power display driving circuit performing internal encoding and decoding and operating method thereof

1. A display driving circuit for outputting a still image, the display driving circuit comprising:

a memory configured to store an input bit stream encoded by a first encoder based on said still image;

a normal data path including a first decoder;

a low-power data path including a second decoder;

a controller configured to selected one of the normal data path and the low-power data path through which output frame data in a second frame period passes according to whether internal encoding is successful in a first frame period,

wherein, when the internal encoding is successful, the controller is configured to perform internal encoding in the second frame period, to store a generated internal bit stream in the memory, to allow the internal bit stream to pass through the low-power data path to generate the output frame data, and

when the internal encoding fails, the controller is configured to generate the output frame data by allowing the input bit stream to pass through the normal data path in the second frame period, to change an encoding setting of an internal encoder, and to repeat the internal encoding.

2. The display driving circuit of claim 1 , wherein the normal data path includes:

the first decoder which is configured to decode the input bit stream to generate frame data; and

a plurality of image processors configured to perform image processing on the frame data to generate a plurality of segments of processed data, and

the controller is configured to perform the internal encoding on at least one of the segments of the processed data and the frame data.

3. The display driving circuit of claim 2 , wherein, as the internal encoding on a first processed data, which have passed through first to third of said plurality of image processors, in the first frame period fails,

the controller is configured to repeat the internal encoding on a second processed data which have passed through the first and second of said plurality of image processors in the second frame period.

4. The display driving circuit of claim 2 , wherein, as the internal encoding on a first processed data, which have passed through first to third of said plurality of image processors, in the first frame period fails,

the controller is configured to repeat the internal encoding on a second processed data which have passed through the first to fourth of said plurality of image processors in the second frame period.

5. The display driving circuit of claim 2 , wherein, as the internal encoding on first processed data in the first frame period fails,

the controller is configured to generate data to be encoded by altering a bit depth of the first processed data and to repeat the internal encoding on the data to be encoded in the second frame period.

6. The display driving circuit of claim 5 , wherein the controller is configured to generate the data to be encoded by reducing the bit depth of the first processed data.

7. The display driving circuit of claim 6 , wherein the controller is configured to store a first internal bit stream generated as a result of repeating the internal encoding in the second frame period in the memory, and

to perform internal decoding on the first internal bit stream and to restore the bit depth of the first internal data.

8. The display driving circuit of claim 1 , wherein, as the internal encoding of processed data generated through the normal data path in the first frame period is successful,

the controller is configured to turn off power to the normal data path in the second frame period.

9. The display driving circuit of claim 1 , wherein the low-power path further includes:

the decoder which is configured to decode the internal bit stream to generate frame data; and

a plurality of first image processors configured to perform image processing on the frame data.

10. The display driving circuit of claim 9 , wherein the internal bit stream is generated based on processed data which have passed through second image processors, to the exclusion of said first image processors.

11. The display driving circuit of claim 10 , wherein an operation of the second image processors is performed before an operation of the first image processors.

12. The display driving circuit of claim 10 , wherein the controller is configured to turn off power of the second image processors in the second frame period.

13. The display driving circuit of claim 1 , further comprising:

an asynchronous buffer configured to temporarily store the internal bit stream,

wherein, in the second frame period, if the internal encoding fails, the controller is configured to change an output frequency of the asynchronous buffer.

14. The display driving circuit of claim 1 , wherein a number of image processors in the normal data path is greater than a number of image processors in the low-power data path.

15. A method of operating a display driving circuit outputting a still image, the method comprising:

generating a plurality of segments of frame data based on an input bit stream in a first frame period;

determining at least one of the segments of frame data as data to be encoded, and performing internal encoding on the data to be encoded;

altering at least one of the data to be encoded and an encoding setting when the internal encoding fails; and

repeating the internal encoding in a second frame period,

wherein the altering includes changing a bit depth of the data to be encoded.

16. The method of claim 15 , wherein, in the repeating of said internal encoding, first frame data generated through first and second image processors is designated as said data to be encoded, and

in the altering, the data to be encoded is changed into second frame data generated through first to third image processors.

17. The method of claim 15 , wherein, in the repeating of internal encoding, first frame data generated through first to third image processors is designated as said data to be encoded, and

in the altering, the data to be encoded is changed into second frame data generated through first and second image processors.

18. The method of claim 15 , further comprising:

storing an internal bit stream generated by repeating the internal encoding in the second frame period; and

restoring a bit depth of the internal bit stream in a third frame period.

19. The method of claim 15 , wherein the display driving circuit operates in a low-power mode, and

the method further comprises:

storing an internal bit stream generated by repeating the internal encoding in the second frame period in a memory; and

turning off a decoder and at least one image processor through which the internal bit stream has passed.

20. A display driving circuit comprising:

a memory configured to store an input bit stream;

a first decoder configured to decode the input bit stream to generate first frame data;

a plurality of image processors configured to perform image processing on the first frame data to generate a plurality of segments of processed data;

an internal encoder configured to perform internal encoding on at least one of the segments of processed data;

an internal decoder configured to decode the internal bit stream stored in the memory and output the decoded bit stream when the internal encoding is successful; and

a controller configured to change an encoding setting of the internal encoder and to control the internal encoder to repeat the internal encoding, when the internal encoding fails,

wherein the changing the encoding setting of the internal encoder includes changing a bit depth of the processed data to be encoded.