Partial subtractive supervia enabling hyper-scaling
View Patent ↗A semiconductor device includes an upper section of a supervia formed via subtractive etching and a lower section of the supervia formed via damascene processing. The supervia connects non-adjacent interconnect wiring. The lower section and the upper section of the supervia each define a generally cone-shaped configuration. A distal end of the lower section of the supervia is non-obtuse. Moreover, the lower section of the supervia is formed in a V 0 level and the upper section of the supervia is formed in a M 1 /V 1 metallization level.
1. A semiconductor device comprising:
an upper section of a supervia, formed via subtractive etching, that defines a generally cone-shaped configuration; and
a lower section of the supervia, formed via damascene processing, that defines a generally cone-shaped configuration,
wherein the supervia connects non-adjacent interconnect wiring.
2. The semiconductor device of claim 1 , wherein a distal end of the lower section of the supervia is non-obtuse.
3. The semiconductor device of claim 1 , wherein a distal end of the lower section of the supervia is generally flat.
4. The semiconductor device of claim 1 , wherein the lower section of the supervia is formed in a V 0 level and the upper section of the supervia is formed in a M 1 /V 1 metallization level.
5. The semiconductor device of claim 1 , wherein a maximum width of the lower section of the supervia is equal to a maximum width of the upper section of the supervia.
6. The semiconductor device of claim 1 , wherein a maximum width of the upper section of the supervia is greater than a maximum width of the lower section of the supervia.
7. A semiconductor device comprising:
an upper section of a supervia, formed via subtractive etching, that defines a generally cone-shaped configuration; and
a lower section of the supervia formed, via damascene processing, that defines a generally cone-shaped configuration,
wherein a maximum width of the upper section of the supervia is greater than a maximum width of the lower section of the supervia.
8. The semiconductor device of claim 7 , wherein the supervia connects non-adjacent interconnect wiring.
9. The semiconductor device of claim 7 , wherein a distal end of the lower section of the supervia is non-obtuse.
10. The semiconductor device of claim 7 , wherein a distal end of the lower section of the supervia is generally flat.
11. The semiconductor device of claim 7 , wherein the lower section of the supervia is formed in a V 0 level and the upper section of the supervia is formed in a M 1 /V 1 metallization level.
12. A method comprising:
forming an upper section of a supervia via subtractive etching to define a generally cone-shaped configuration of the upper section;
forming a lower section of the supervia via damascene processing to define a generally cone-shaped configuration of the lower section; and
enabling the supervia to connect non-adjacent interconnect wiring.
13. The method of claim 12 , wherein a distal end of the lower section of the supervia is generally flat.
14. The method of claim 12 , wherein a distal end of the lower section of the supervia is non-obtuse.
15. The method of claim 12 , wherein the lower section of the supervia is formed in a V 0 level and the upper section of the supervia is formed in a M 1 /V 1 metallization level.
16. The method of claim 12 , wherein a maximum width of the lower section of the supervia is equal to a maximum width of the upper section of the supervia.
17. The method of claim 12 , wherein a maximum width of the upper section of the supervia is greater than a maximum width of the lower section of the supervia.