IP Library › Granted Patent US 11,908,805
Granted Patent B2
US 11,908,805 · App. 17/071,951 · Granted Feb 20, 2024

Semiconductor packages and associated methods with solder mask opening(s) for in-package ground and conformal coating contact

Inventors: Avishesh Dhakal (Meridian, ID); Gary A. Monroe (Plano, TX)
Assignee: Micron Technology, Inc.
H01L23/552H01L21/4853H01L21/4857H01L21/561H01L21/565H01L21/78H01L23/3128H01L23/3135H01L23/49822H01L23/49838
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Quick Facts
Patent No.
US 11,908,805
App. No.
17/071,951
Granted
Feb 20, 2024
Kind
B2
Abstract

Semiconductor devices with a conformal coating in contact with a ground plane at a bottom side of the semiconductor devices and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a first surface of a package substrate. The semiconductor device can also include a molded material covering at least a portion of the package substrate and the semiconductor die. The semiconductor device can also include a ground plane in the package substrate and exposed through an opening in a second surface of the package substrate opposite the first surface. The semiconductor device can also include a conformal coating coupled to the ground plane through the opening that can shield the semiconductor device from electromagnetic interference.

Claims (27)

1. A semiconductor device, comprising:

a package substrate having a ground plane, a first surface having a die attach area, and a second surface opposite the first surface; and

a conformal coating positioned over a side of the first surface opposite the second surface, and extending along a side of the package substrate from the first surface to the second surface where the conformal coating is electrically coupled to the ground plane through an opening in the second surface of the package substrate.

2. The semiconductor device of claim 1 , wherein the ground plane is recessed within the opening in the second surface of the package substrate.

3. The semiconductor device of claim 2 , wherein the conformal coating is electrically coupled directly to the ground plane.

4. The semiconductor device of claim 2 , wherein the package substrate further includes a conductive trace that extends from the ground plane to the second surface of the package substrate, and wherein the conformal coating is electrically coupled to the ground plane via the conductive trace.

5. The semiconductor device of claim 4 , wherein the conformal coating is electrically coupled to the conductive trace at the second surface of the package substrate.

6. The semiconductor device of claim 1 , wherein the opening is a trench or moat, and wherein the semiconductor device includes solder mask between the package substrate and the conformal coating.

7. The semiconductor device of claim 1 , wherein the opening extends around a perimeter of the package substrate.

8. The semiconductor device of claim 1 , wherein

the semiconductor device further comprises a molded material covering at least a portion of the package substrate;

the molded material includes a top surface;

the molded material and the package substrate include a plurality of side surfaces; and

the conformal coating coats the top surface and the plurality of side surfaces.

9. The semiconductor device of claim 1 , further comprising a semiconductor die coupled to the first surface of the package substrate.

10. The semiconductor device of claim 9 , wherein the conformal coating is configured to shield the semiconductor die from electromagnetic interference.

11. A package substrate, comprising:

a plurality of substrates and/or dielectric materials, wherein the plurality of substrates and/or dielectric materials includes:

a first substrate and/or dielectric material having a first surface, the first surface (i) being a topmost surface of the package substrate relative to all other substrates and/or dielectric materials of the plurality of substrates and/or dielectric materials, (ii) located at a first side of the package substrate, and (iii) including a die attach area, and

a second substrate and/or dielectric material having a second surface, the second surface (i) being a bottommost surface of the package substrate relative to all other substrates and/or dielectric materials of the plurality of substrates and/or dielectric materials and (ii) located at a second side of the package substrate opposite the first side; and

a ground plane positioned between the first surface and the second surface, wherein the ground plane is exposed via an opening in the bottommost surface.

12. The package substrate of claim 11 , wherein:

the ground plane is recessed within the opening in the second surface of the package substrate; and/or

the package substrate further includes a conductive trace that extends from the ground plane to the second surface of the package substrate.

13. The package substrate of claim 12 , wherein:

the opening is a trench or moat; and/or

the opening extends around a perimeter of the package substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2020
From: DHAKAL, AVISHESH; MONROE, GARY A.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 054072/0094 →
Continuity (2)
Continuation 16234068 · Dec 27, 2018
Related Publication 20210028123A1 · Jan 28, 2021