Methods of forming semiconductor structures
Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.
1. A method of forming a semiconductor structure, the method comprising:
patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor;
pre-cleaning the substrate;
depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD);
optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor;
forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor;
forming a second barrier layer on the molybdenum silicide (MoSi) layer; and
annealing the semiconductor structure.
2. The method of claim 1 , wherein the n transistor comprises silicon (Si) doped with phosphorous (P), and the p transistor comprises silicon germanium (SiGe) doped with boron (B).
3. The method of claim 1 , wherein the first barrier layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN).
4. The method of claim 3 , wherein the first barrier layer is formed by one or more of an atomic layer deposition (ALD) process or a physical vapor deposition (PVD) process.
5. The method of claim 1 , wherein the second barrier layer comprises molybdenum nitride (MoN), nitridated molybdenum silicide (MoSi) and a PVD metal film.
6. The method of claim 1 , further comprising independently filling the first opening and the second opening with a gapfill material.
7. The method of claim 6 , wherein the gapfill material is substantially free of voids or seams.
8. The method of claim 6 , wherein the gapfill material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co) and ruthenium (Ru).
9. The method of claim 1 , wherein annealing the semiconductor structure forms one or more of ohmic and pseudo-ohmic contacts on the n transistor and on the p transistor.
10. The method of claim 1 , wherein the titanium silicide (TiSi) layer on the n transistor has a Schottky barrier height in a range of from about 0.4 eV to about 0.55 eV.
11. A method of forming a semiconductor structure, the method comprising:
patterning a substrate to form a first opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor;
pre-cleaning the substrate;
depositing a titanium silicide (TiSi) layer on the n transistor by plasma-enhanced chemical vapor deposition (PECVD);
filling the first opening with a first gapfill material;
forming a mask layer on a top surface of the n transistor;
patterning the substrate to form a second opening over the p transistor;
forming a molybdenum silicide (MoSi) layer on the p transistor;
annealing the semiconductor structure; and
filling the second opening with a second gapfill material.
12. The method of claim 11 , wherein the mask layer comprises one or more of a hard mask layer and a photoresist layer.
13. The method of claim 11 , further comprising forming a barrier layer on the titanium silicide (TiSi) layer on the n transistor.
14. The method of claim 13 , further comprising depositing the barrier layer on the molybdenum silicide (MoSi) layer on the p transistor and selectively removing the barrier layer from the p transistor.
15. The method of claim 13 , wherein the barrier layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN).
16. The method of claim 11 , wherein the first gapfill material and the second gapfill material independently comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co) and ruthenium (Ru).