Double gate ferroelectric field effect transistor devices and methods for forming the same

1. A semiconductor structure, comprising:

a first dielectric material layer;

a first gate electrode laterally surrounded by the first dielectric material layer;

a multilayer structure over the first dielectric material layer and the first gate electrode, the multilayer structure comprising:

a first ferroelectric material layer;

a semiconductor channel layer over the first ferroelectric material layer; and

a second ferroelectric material layer over the semiconductor channel layer; and

source and drain electrodes contacting the semiconductor channel layer; and

a second gate electrode over the second ferroelectric material layer.

2. The semiconductor structure of claim 1 , wherein the source and drain electrodes comprise:

an upper source electrode that extends through the second ferroelectric material layer and contacts an upper surface of the semiconductor channel layer; and

an upper drain electrode that extends through the second ferroelectric material layer and contacts the upper surface of the semiconductor channel layer.

3. The semiconductor structure of claim 2 , wherein each of the upper source electrode and the upper drain electrode are laterally surrounded by a dielectric material spacer layer.

4. The semiconductor structure of claim 2 , further comprising:

a second dielectric material layer over the second ferroelectric material layer and laterally surrounding the second gate electrode, the upper source electrode and the upper drain electrode extending through the second dielectric material layer.

5. The semiconductor structure of claim 4 , wherein the source and drain electrodes further comprise:

a bottom source electrode that extends from the first dielectric material layer through the first ferroelectric material layer and contacts a bottom surface of the semiconductor channel layer; and

a bottom drain electrode that extends from the first dielectric material layer through the first ferroelectric material layer and contacts the bottom surface of the semiconductor channel layer.

6. The semiconductor structure of claim 5 , wherein each of the bottom source electrode and the bottom drain electrode are laterally surrounded by a dielectric material spacer layer.

7. The semiconductor structure of claim 1 , wherein the semiconductor channel layer comprises an oxide semiconductor material having a formula M x M′ y Zn z O where 0<(x, y, z)<1, M is a first metal selected from a group consisting of indium (In) and tin (Sn) and combinations thereof, M′ is a second metal selected from a group consisting of gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd), and combinations thereof.

8. The semiconductor structure of claim 1 , wherein the first ferroelectric material layer and the second ferroelectric material layer comprise hafnium oxide-based ferroelectric materials.

9. The semiconductor structure of claim 1 , wherein at least one of a seed layer and a stress layer are located between the first gate electrode and a bottom surface of the first ferroelectric material layer.

10. The semiconductor structure of claim 1 , wherein an insulating layer is located between an upper surface of the first ferroelectric material layer and a bottom surface of the semiconductor channel layer, and at least one of an insulating layer and a seed layer are located between an upper surface of the semiconductor channel layer and a bottom surface of the second ferroelectric material layer.

11. The semiconductor structure of claim 1 , further comprising a seed layer located between an upper surface of the second ferroelectric material layer and a bottom surface of the second gate electrode.

12. The semiconductor structure of claim 1 , wherein the first gate electrode and the second gate electrode are coupled to a common voltage in a common gate control mode.

13. The semiconductor structure of claim 1 , wherein the first gate electrode and the second gate electrode are coupled to different voltages in a separated gate control mode.

14. A semiconductor structure, comprising:

a gate electrode;

a semiconductor channel layer, wherein the semiconductor channel layer comprises:

a first alternating stack of first sublayers and second sublayers, the first sublayers having a different composition than the second sublayers,

a third sublayer over the first alternating stack of first and second sublayers, the third sublayer having a different composition than the first sublayers and the second sublayers, and

a second alternating stack of the first sublayers and the second sublayers over the third sublayer, wherein each of the first sublayers of the first alternating stack and the second alternating stack comprises a combination of a first metal oxide material, MO x , and a second metal oxide material, M′O x , and each second sublayer of the first alternating stack and the second alternating stack comprises zinc oxide, and the third sublayer comprises a combination of a first metal oxide material, MO x , a second metal oxide material, M′ O x , and zinc oxide, and wherein M is a first metal selected from a group consisting of indium (In) and tin (Sn) and combinations thereof, and M′ is a second metal selected from a group consisting of gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd), and combinations thereof;

a ferroelectric material layer located between the gate electrode and a surface of the semiconductor channel layer, wherein the ferroelectric material layer and the semiconductor channel layer have a same width dimension, and a width dimension of the gate electrode is less than the width dimensions of the ferroelectric material layer and the semiconductor channel layer; and

source and drain electrodes contacting the semiconductor channel layer.

15. The semiconductor structure of claim 14 , wherein a lowermost sublayer of the semiconductor channel layer is a first sublayer of the first alternating stack of first sublayers and second sublayers, and an uppermost sublayer of the semiconductor channel layer is a first sublayer of the second alternating stack of first sublayers and second sublayers, and wherein the third sublayer is contacted by a second sublayer of the second alternating stack of first sublayers and second sublayers on an upper surface of the third sublayer, and the third sublayer is contacted by a second sublayer of the first alternating stack of first sublayers and second sublayers on a bottom surface of the third sublayer.

16. The semiconductor structure of claim 14 , wherein the gate electrode comprises a first gate electrode and the ferroelectric material layer comprises a first ferroelectric material layer located between the first gate electrode and a first surface of the semiconductor channel layer, the semiconductor structure further comprising:

a second gate electrode; and

a second ferroelectric material layer located between the second gate electrode and a second surface of the semiconductor channel layer.

17. A method of fabricating a semiconductor structure, comprising:

forming a first gate electrode laterally surrounded by a first dielectric material layer;

forming a first ferroelectric material layer over the first gate electrode and the first dielectric material layer;

forming a semiconductor channel layer over the first ferroelectric material layer;

forming source and drain electrodes contacting the semiconductor channel layer;

forming a second ferroelectric material layer over the semiconductor channel layer; and

forming a second gate electrode over the second ferroelectric material layer.

18. The method of claim 17 , wherein forming source and drain electrodes contacting the semiconductor channel layer comprises forming upper source and drain electrodes contacting an upper surface of the semiconductor channel layer, the method further comprising:

forming bottom source and drain electrodes contacting a bottom surface of the semiconductor channel layer.

19. The method of claim 18 , further comprising:

forming dielectric material spacer layers laterally surrounding at least one of the upper source and drain electrodes and the bottom source and drain electrodes.

20. The method of claim 17 , wherein forming the semiconductor channel layer comprises:

forming a first alternating stack of first and second sublayers including a set of first sublayers that each include a combination of a first metal oxide material, MO x , and a second metal oxide material, M′ OX, and a set of second sublayers including zinc oxide;

forming a third sublayer over the first alternating stack, wherein the third sublayer includes a combination of a first metal oxide material, MO x , a second metal oxide material, M′O x , and zinc oxide; and

forming a second alternating stack of first and second sublayers over the third sublayer including a set of first sublayers that each include a combination of a first metal oxide material, MO x , and a second metal oxide material, M′O x , and a set of second sublayers including zinc oxide, wherein M is a first metal selected from a group consisting of indium (In) and tin (Sn) and combinations thereof, M′ is a second metal selected from a group consisting of gallium (Ga), hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), gadolinium (Gd), and combinations thereof.