Semiconductor memory device, electronic system including the same, and method of fabricating the same

1. A semiconductor memory device, comprising:

a mold structure including a plurality of wordlines, which are sequentially stacked on a front side of a first substrate, and a string selection line and a stopper line, which are sequentially stacked on the plurality of wordlines;

a channel structure extending in a vertical direction, which intersects the front side of the first substrate, to penetrate the mold structure;

a block separation structure extending in a first direction, which intersects the vertical direction, to cut the mold structure;

a protective structure interposed between the block separation structure and the stopper line, and not between the block separation structure and the string selection line and not between the block separation structure and the plurality of wordlines;

a string separation structure extending in the first direction to cut the string selection line and the stopper line;

a bitline extending in a second direction, which intersects the vertical direction and the first direction, on the mold structure; and

a bitline contact connecting the channel structure and the bitline,

wherein the protective structure has a lowermost surface located at a depth above the string selection line, and the block separation structure directly contacts the string selection line and the plurality of word lines below the protective structure.

2. The semiconductor memory device of claim 1 , wherein the string separation structure at least partially overlaps with the channel structure.

3. The semiconductor memory device of claim 1 , wherein the stopper line and the protective structure include materials different from each other.

4. The semiconductor memory device of claim 3 , wherein

the stopper line includes silicon nitride, and

the protective structure includes silicon oxide.

5. The semiconductor memory device of claim 1 , wherein the string separation structure includes silicon oxide.

6. The semiconductor memory device of claim 1 , wherein a top surface of the string separation structure is positioned higher than a top surface of the protective structure.

7. The semiconductor memory device of claim 1 , wherein a top surface of the bitline contact is positioned higher than a top surface of the string separation structure.

8. The semiconductor memory device of claim 1 , wherein the bitline contact is spaced apart from the string separation structure.

9. The semiconductor memory device of claim 1 , further comprising:

a second substrate including a front side that faces the front side of the first substrate; and

a peripheral circuit element on the front side of the second substrate.

10. The semiconductor memory device of claim 9 , wherein the bitline is interposed between the first substrate and the second substrate.

11. The semiconductor memory device of claim 1 , wherein an uppermost surface of the protective structure is horizontally aligned with an uppermost surface of the block separation structure.

12. A semiconductor memory device, comprising:

a mold structure including a plurality of wordlines, which are sequentially stacked on a front side of a substrate, and a string selection line and a stopper line, which are sequentially stacked on the plurality of wordlines;

a first channel structure extending in a vertical direction, which intersects the front side of the substrate, to penetrate the mold structure;

a string separation structure extending in a first direction, which intersects the vertical direction, to cut the string selection line and the stopper line, the string separation structure at least partially overlapping with the first channel structure;

a bitline extending in a second direction, which intersects the vertical direction and the first direction, on the mold structure;

a first bitline contact connecting the first channel structure and the bitline;

a block separation structure extending in the first direction to cut the mold structure; and

a protective structure interposed between the block separation structure and the stopper line, and not between the block separation structure and the string selection line and not between the block separation structure and the plurality of wordlines,

wherein the first bitline contact is shifted from a center of the first channel structure in a direction away from the string separation structure, and

wherein the protective structure has a lowermost surface located at a depth above the string selection line, and the block separation structure directly contacts the string selection line and the plurality of word lines below the protective structure.

13. The semiconductor memory device of claim 12 , wherein the first bitline contact is in contact with a top surface of the stopper line.

14. The semiconductor memory device of claim 12 , wherein the first bitline contact is in contact with a side surface of the first channel structure.

15. The semiconductor memory device of claim 12 , further comprising:

a contact stud connecting the first bitline contact and the bitline,

wherein the contact stud is shifted from a center of the first bitline contact in a direction toward the string separation structure.

16. The semiconductor memory device of claim 12 , further comprising:

a second channel structure extending in the vertical direction to penetrate the mold structure, the second channel structure being spaced apart from the first channel structure with the string separation structure interposed therebetween,

wherein the string separation structure at least partially overlaps with the second channel structure.

17. The semiconductor memory device of claim 16 , further comprising:

a second bitline contact connected to the second channel structure,

wherein the second bitline contact is shifted from a center of the second channel structure in a direction away from the string separation structure.

18. The semiconductor memory device of claim 12 , further comprising:

a second channel structure extending in the vertical direction to penetrate the mold structure, the second channel structure being spaced apart from the string separation structure with the first channel structure interposed therebetween;

a second bitline contact connecting the second channel structure and the bitline;

a third channel structure extending in the vertical direction to penetrate the mold structure, the third channel structure being spaced apart from the first channel structure with the string separation structure interposed therebetween; and

a third bitline contact connecting the third channel structure and the bitline,

wherein a distance between the first bitline contact and second bitline contact is smaller than a distance between the first bitline contact and third bitline contact.

19. The semiconductor memory device of claim 18 , wherein the first channel structure to third channel structure are arranged at regular intervals in the first direction.

20. An electronic system, comprising:

a main substrate;

a semiconductor memory device on the main substrate; and

a controller electrically connected to the semiconductor memory device, on the main substrate,

wherein the semiconductor memory device includes:

a mold structure including a plurality of wordlines, which are sequentially stacked on a front side of a substrate, and a string selection line and a stopper line, which are sequentially stacked on the wordlines;

a channel structure extending in a vertical direction, which intersects the front side of the substrate, to penetrate the mold structure;

a string separation structure extending in a first direction, which intersects the vertical direction, to cut the string selection line and the stopper line, the string separation structure at least partially overlapping with the channel structure;

a bitline extending in a second direction, which intersects the vertical direction and the first direction, on the mold structure;

a bitline contact connecting the channel structure and the bitline, the bitline contact being shifted from a center of the channel structure in a direction away from the string separation structure;

a peripheral circuit element connected to the bitline contact;

an input/output pad connecting the controller and the peripheral circuit element;

a block separation structure extending in the first direction to cut the mold structure; and

a protective structure interposed between the block separation structure and the stopper line, and not between the block separation structure and the string selection line and not between the block separation structure and the plurality of wordlines,

wherein the protective structure has a lowermost surface located at a depth above the string selection line, and that the block separation structure directly contacts the string selection line and the plurality of word lines below the protective structure.