Phase change memory cell with ovonic threshold switch
A structure including a bottom electrode, a phase change material layer vertically aligned and an ovonic threshold switching layer vertically aligned above the phase change material layer. A structure including a bottom electrode, a phase change material layer and an ovonic threshold switching layer vertically aligned above the phase change material layer, and a first barrier layer physically separating the ovonic threshold switching layer from a top electrode. A method including forming a structure including a liner vertically aligned above a first barrier layer, the first barrier layer vertically aligned above a phase change material layer, the phase change material layer vertically aligned above a bottom electrode, forming a dielectric surrounding the structure, and forming an ovonic threshold switching layer on the first barrier layer, vertical side surfaces of the first buffer layer are vertically aligned with the first buffer layer, the phase change material layer and the bottom electrode.
1. A method comprising:
forming a bottom electrode on a substrate;
forming a phase change material layer on the bottom electrode;
forming an ovonic threshold switching layer above the phase change material layer, wherein vertical sidewalls of the bottom electrode and the phase change material layer are aligned with one another; and
forming a first buffer layer above the ovonic threshold switching layer, wherein a width of the first buffer layer is greater than a width of the ovonic threshold switching layer.
2. The method according to claim 1 , further comprising:
forming a top electrode above the first buffer layer, the first buffer layer physically separating the ovonic threshold switching layer and the top electrode, wherein
a width of the ovonic threshold switching layer is less than a width of the top electrode.
3. The method according to claim 2 , wherein
a width of the phase change material layer is less than the width of the top electrode.
4. The method according to claim 1 , further comprising:
forming a dielectric surrounding the bottom electrode, the phase change material layer, and the ovonic threshold switching layer, wherein a portion of the first buffer layer covers an upper horizontal portion of the dielectric.
5. The method according to claim 1 , further comprising:
forming a second buffer layer, the second buffer layer physically separating the ovonic threshold switching layer and the phase change material layer.
6. The method according to claim 1 , further comprising:
forming an array of structures, wherein the structures are wired together forming word lines and bit lines.
7. A method comprising:
forming a bottom electrode on a substrate;
forming a phase change material layer on the bottom electrode;
forming a first buffer layer on the phase change material layer;
forming an ovonic threshold switching layer above the first buffer layer, wherein vertical sidewalls of the bottom electrode, the phase change material layer and the ovonic threshold switching layer are aligned with one another; and
forming a second buffer layer above the ovonic threshold switching layer, wherein a width of the second buffer layer is greater than a width of the ovonic threshold switching layer.
8. The method according to claim 1 , further comprising:
forming a top electrode above the second buffer layer, the second buffer layer physically separating the ovonic threshold switching layer and the top electrode.
9. The method according to claim 8 , wherein
a width of the ovonic threshold switching layer is less than a width of the top electrode.
10. The method according to claim 2 , wherein
a width of the phase change material layer is less than the width of the top electrode.
11. The method according to claim 7 , further comprising:
forming a dielectric surrounding the bottom electrode, the phase change material layer, and the ovonic threshold switching layer.
12. The method according to claim 7 , wherein a portion of the second buffer layer covers an upper horizontal portion of the dielectric.
13. The method according to claim 7 , further comprising:
forming an array of structures, wherein the structures are wired together forming word lines and bit lines.
14. A method comprising:
forming a bottom electrode on a substrate;
forming a phase change material layer on the bottom electrode;
forming a first buffer layer on the phase change material layer;
forming an ovonic threshold switching layer above the first buffer layer, wherein vertical sidewalls of the bottom electrode, the phase change material layer and the ovonic threshold switching layer are aligned with one another; and
forming a second buffer layer above the ovonic threshold switching layer, wherein a width of the second buffer layer is greater than a width of the ovonic threshold switching layer,
wherein the second buffer layer covers an upper horizontal portion of a first dielectric surrounding the phase change material layer, the first buffer layer and the ovonic threshold switching layer.
15. The method according to claim 14 , further comprising:
forming a top electrode above the second buffer layer, the second buffer layer physically separating the ovonic threshold switching layer and the top electrode.
16. The method according to claim 15 , wherein
a width of the ovonic threshold switching layer is less than a width of the top electrode.
17. The method according to claim 16 , wherein
a width of the phase change material layer is less than the width of the top electrode.
18. The method according to claim 14 , further comprising:
forming a dielectric surrounding the bottom electrode, the phase change material layer, and the ovonic threshold switching layer.
19. The method according to claim 18 , wherein a portion of the second buffer layer covers an upper horizontal portion of the dielectric.
20. The method according to claim 14 , further comprising:
forming an array of structures, wherein the structures are wired together forming word lines and bit lines.