Reflective mask blank, reflective mask, and method for manufacturing semiconductor device
A reflective mask blank comprises a substrate; a multilayer reflective film which is formed on the substrate and reflects EUV light; and a layered film which is formed on the multilayer reflective film. The layered film has an absolute reflectance of 2.5% or less with respect to EUV light, and comprises a first layer and a second layer formed on the first layer; and the first layer comprises a phase shift film which shifts the phase of EUV light. Alternatively, the layered film is a phase shift film which comprises a first layer and a second layer formed on the first layer, and which shifts the phase of EUV light; and the first layer comprises an absorption layer that has an absolute reflectance of 2.5% or less with respect to EUV light.
1. A reflective mask blank comprising:
a substrate;
a multilayer reflective film that is formed on the substrate and configured to reflect EUV light; and
a layered film formed on the multilayer reflective film,
wherein the layered film includes a first layer and a second layer formed on the first layer, and
wherein the layered film has an absolute reflectance of 2.5% or less with respect to the EUV light, and
wherein the first layer includes a phase shift film configured to shift a phase of the EUV light.
2. The reflective mask blank according to claim 1 , wherein the second layer is configured to reduce the absolute reflectance of the layered film to 2.5% or less by optical interference.
3. The reflective mask blank according to claim 2 , wherein the second layer has a film thickness of 1 nm or more and 20 nm or less and a refractive index n of 0.85 or more and 0.96 or less.
4. The reflective mask blank according to claim 2 , wherein the second layer contains ruthenium (Ru).
5. The reflective mask blank according to claim 1 , wherein the second layer is configured to reduce the absolute reflectance of the layered film to 2.5% or less by absorbing light.
6. The reflective mask blank according to claim 5 , wherein the second layer has a film thickness of 5 nm or more and 70 nm or less and an extinction coefficient k of 0.02 or more.
7. The reflective mask blank according to claim 5 , wherein the second layer contains at least one element selected from the group consisting of tantalum (Ta), chromium (Cr), cobalt (Co), and nickel (Ni).
8. The reflective mask blank according to claim 1 , wherein the first layer has a relative reflectance of 3% or more and 40% or less and is configured to cause a phase difference of 160 to 200° with respect to the EUV light.
9. The reflective mask blank according to claim 1 , wherein the first layer has a film thickness of 5 nm or more and 70 nm or less and a refractive index n of 0.85 or more and 0.96 or less.
10. The reflective mask blank according to claim 1 , wherein the first layer contains at least one element selected from the group consisting of tantalum (Ta), titanium (Ti), ruthenium (Ru), and chromium (Cr).
11. The reflective mask blank according to claim 1 , further comprising a protective film between the multilayer reflective film and the first layer, wherein
the protective film contains at least one material selected from the group consisting of a material containing ruthenium (Ru), a material containing silicon (Si) and oxygen (O), a material containing yttrium (Y) and oxygen (O), and a material containing chromium (Cr).
12. A reflective mask having a layered film pattern in which the layered film in the reflective mask blank according to claim 1 is patterned.
13. A method for manufacturing a semiconductor device, the method comprising forming a transfer pattern on a semiconductor substrate using the reflective mask according to claim 12 .
14. A reflective mask blank comprising:
a substrate,
a multilayer reflective film that is formed on the substrate and configured to reflect EUV light, and
a layered film formed on the multilayer reflective film,
wherein the layered film is a phase shift film that includes a first layer and a second layer formed on the first layer, and
wherein the phase shift film is configured to shift a phase of the EUV light, and
wherein the first layer includes an absorption layer having an absolute reflectance of 2.5% or less with respect to the EUV light.
15. The reflective mask blank according to claim 14 , wherein the second layer is configured to shift a phase of EUV light reflected by the layered film by optical interference.
16. The reflective mask blank according to claim 14 , wherein the second layer has a film thickness of 1 nm or more and 20 nm or less and a refractive index n of 0.85 or more and 0.96 or less.
17. The reflective mask blank according to claim 14 , wherein the second layer contains ruthenium (Ru).
18. The reflective mask blank according to claim 14 , wherein the first layer has a film thickness of 5 nm or more and 70 nm or less and an extinction coefficient k of 0.02 or more.
19. The reflective mask blank according to claim 14 , wherein the first layer contains at least one element selected from the group consisting of tantalum (Ta), chromium (Cr), cobalt (Co), and nickel (Ni).
20. The reflective mask blank according to claim 14 , wherein the layered film has a relative reflectance of 3% or more and 40% or less and is configured to cause a phase difference of 160 to 200° with respect to the EUV light.
21. The reflective mask blank according to claim 14 , further comprising a protective film between the multilayer reflective film and the first layer, wherein
the protective film contains at least one material selected from the group consisting of a material containing ruthenium (Ru), a material containing silicon (Si) and oxygen (O), a material containing yttrium (Y) and oxygen (O), and a material containing chromium (Cr).
22. A reflective mask having a layered film pattern in which the layered film in the reflective mask blank according to claim 14 is patterned.
23. A method for manufacturing a semiconductor device, the method comprising forming a transfer pattern on a semiconductor substrate using the reflective mask according to claim 22 .