IP Library › Granted Patent US 11,914,714
Granted Patent B2
US 11,914,714 · App. 17/159,349 · Granted Feb 27, 2024

Information processing apparatus and start-up method of the same

Inventor: Yoshihisa Nomura (Chiba, JP)
Assignee: Canon Kabushiki Kaisha
G06F21/572H04L9/30H04L9/3236H04N1/00938G06F2221/033H04L9/3247H04N2201/0094
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Quick Facts
Patent No.
US 11,914,714
App. No.
17/159,349
Granted
Feb 27, 2024
Kind
B2
Abstract

An information processing apparatus includes a first CPU, a second CPU, a first nonvolatile memory that stores a boot program to be executed by the first CPU at a time of start-up, and a second nonvolatile memory that stores a first boot program and a second boot program for verifying a program. The first CPU determines whether or not a verification method is set in the first nonvolatile memory, and if not, the first CPU executes the first boot program, and writes the setting of the verification method to the second nonvolatile memory. If the verification method is set, the first CPU executes the second boot program in accordance with the setting, and when the processing of the second boot program is normally ended, the second CPU starts up the information processing apparatus.

Claims (25)

1. An information processing apparatus comprising:

a first CPU;

a second CPU;

a first nonvolatile memory that stores a boot program to be executed by the first CPU at a time of start-up; and

a second nonvolatile memory that stores a first boot program and a second boot program for verifying a program,

wherein the first CPU determines whether or not a verification method indicating encryption is set in the first nonvolatile memory as a setting for verifying alteration of a program, and if the verification method has not been set, executes the first boot program, and writes the setting of the verification method to the second nonvolatile memory, and

if the verification method is set, the first CPU executes the second boot program in accordance with the setting, and when the processing of the second boot program is normally ended, the second CPU starts up the information processing apparatus.

2. The information processing apparatus according to claim 1 , wherein the setting includes a setting of the verification method, a public key for verifying the second boot program, and a header pointer of the second boot program.

3. The information processing apparatus according to claim 1 , wherein, if the verification method is not set, the first CPU performs verification regarding the first boot program using a hash value, and if the verification is successful, executes the first boot program.

4. The information processing apparatus according to claim 2 , wherein, if the verification method is set, the first CPU performs verification regarding the second boot program using the public key included in the setting, and if the verification is successful, executes the second boot program.

5. The information processing apparatus according to claim 1 , wherein the second boot program performs signature verification on BIOS to be executed by the second CPU, and if the signature verification is successful, the reset of the second CPU is released, and the second CPU starts up the information processing apparatus.

6. The information processing apparatus according to claim 1 , wherein the initial value of the setting for verifying alteration of a program indicates a verification method using a hash value.

7. The information processing apparatus according to claim 2 , wherein, if the setting value of the public key is an initial value, the first CPU determines that a verification method indicating encryption is not set as the setting for verifying alteration of a program.

8. The information processing apparatus according to claim 1 , wherein the first CPU, after writing the setting of the verification method to the second nonvolatile memory by executing the first boot program, restarts the information processing apparatus.

9. The information processing apparatus according to claim 1 , wherein the first nonvolatile memory is an OTP-ROM (One Time Programmable ROM).

10. The information processing apparatus according to claim 1 , wherein the second nonvolatile memory is a flash memory.

11. A start-up method of an information processing apparatus including a first CPU, a second CPU, a first nonvolatile memory that stores a boot program to be executed by the first CPU, and a second nonvolatile memory that stores a first boot program and a second boot program for verifying a program, the start-up method comprising:

the first CPU executing the boot program stored in the first nonvolatile memory by, at a time of start-up,

wherein the first CPU determines whether or not a verification method indicating encryption is set in the first nonvolatile memory as a setting for verifying alteration of a program,

if the verification method has not been set, the first CPU executes the first boot program, and writes the setting of the verification method to the first nonvolatile memory,

when the setting of the verification method is written into the first nonvolatile memory, the first CPU restarts the information processing apparatus,

if the verification method has been set, the first CPU executes the second boot program in accordance with the setting, and

if the processing performed by the second boot program is normally ended, the second CPU starts up the information processing apparatus.

12. The start-up method according to claim 11 , wherein if the verification method has not been set, the first CPU performs verification of the first boot program using a hash value, and if the verification is successful, executes the first boot program.

13. The start-up method according to claim 11 , wherein if the verification method has been set, the first CPU performs verification of the second boot program using a public key included in the setting, and if the verification is successful, executes the second boot program.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2021
From: NOMURA, YOSHIHISA
To: CANON KABUSHIKI KAISHA
Reel/Frame 055542/0478 →
Priority Claims (1)
JP 2020-012890 · Jan 29, 2020 · national
Continuity (1)
Related Publication 20210232690A1 · Jul 29, 2021