Secured boot of a processing unit

1. A method for booting a processing device, the method comprising:

generating, by a monotonic counter during a first boot phase, a first count value;

transmitting, by the monotonic counter, the first count value to an access control circuit of a memory;

reading, based on the first count value, first data stored in the memory and associated with the first boot phase;

generating, by the monotonic counter during a second boot phase, a second count value greater than the first count, value;

transmitting, by the monotonic counter, the second count value to the access control circuit of the memory;

preventing, by the access control circuit based on the second count value, reading of the first data; and

reading, based on the second count value, second data stored in the memory and associated with the second boot phase.

2. The method according to claim 1 , wherein the first data comprises first boot codes.

3. The method according to claim 2 , wherein the first boot codes are executed prior to the monotonic counter generating the second count value, the first boot codes comprising an instruction to increment the monotonic counter to cause the generation of the second count value.

4. The method according to claim 1 , wherein the memory is a volatile memory.

5. The method according to claim 1 , wherein the memory is a non-volatile memory.

6. The method according to claim 1 , wherein the access control circuit of the memory is configured to not authorize reading of the first data in response to a count value being greater than the first count value.

7. The method according to claim 1 , further comprising:

prereading, based on the first count value during the first boot phase, the second data stored in the memory and associated with the second boot phase.

8. The method according to claim 1 , wherein:

the first count value corresponds to an initialization value of the monotonic counter upon a first boot of the processing device, and

the method further comprises a second boot of the processing device during which the monotonic counter is initialized to the second count value.

9. The method according to claim 8 , further comprising a third boot of the processing device, after the first boot and the second boot, at which the monotonic counter is initialized again to the first count value in response to a condition on a state of the processing device being satisfied.

10. The method according to claim 9 , wherein the condition on the state of the processing device corresponds to a programming state of one or more bits stored in a non-volatile manner in an area of the memory or of another memory.

11. The method according to claim 1 , further comprising:

reading, prior to generating the second count value and based on the first count value, one or more first encryption keys stored in the memory, the access control circuit of the memory being configured to not authorize reading of the first encryption keys in response to a count value being greater than the first count value.

12. The method according to claim 11 , further comprising:

reading, after generating the second count value and based on the second count value, one or more second encryption keys stored in the memory.

13. A method for booting a processing device, the method comprising:

(a) executing a first boot phase comprising:

generating, by a monotonic counter a first count value,

transmitting, by the monotonic counter, the first count value to an access control circuit of a memory, and

reading, based on the first count value, first data stored in the memory; and

(b) executing a second boot phase comprising:

irreversibly incrementing the monotonic counter to a second count value greater than the first count value,

transmitting, by the monotonic counter, the second count value to the access control circuit of the memory,

preventing, by the access control circuit based on the second count value, reading of the first data, and

reading, based on the second count value, second data stored in the memory and associated with the second boot phase.

14. The method of claim 13 , further comprising:

rebooting the processing device to reset the monotonic counter; and

repeating steps (a) and (b).

15. The method of claim 13 , wherein:

the second data is associated with an isolation level equal to the second count value; and

executing the second boot phase further comprises reading, based on the second count value, third data, the third data being associated with an isolation level greater than the second count value.

16. A data processing device comprising:

a monotonic counter configured to:

generate a first count value for a first boot phase; and

after generating the first count value, generate a second count value for a second boot phase, wherein the second count value is greater than the first count value; and

a memory including an access control circuit and containing first and second boot codes, wherein the access control circuit is configured to:

read, based on the first count value during the first boot phase, the first boot code;

prevent, based on the second count value during the second boot phase, reading of the first boot code; and

read, based on the second count value during the second boot phase, the second boot code.

17. The data processing device of claim 16 , wherein the memory is a volatile memory.

18. The data processing device of claim 16 , wherein the memory is a non-volatile memory.

19. The data processing device of claim 16 , wherein the monotonic counter is further configured to only increment generated count values and to re-initialize based on a condition on a state of the data processing device being satisfied.