Accelerated cryptographic-related processing

1. A computer system for facilitating cryptographic-related processing within a computing environment, the computer system comprising:

a memory; and

a processing circuit in communication with the memory, wherein the computer system is configured to perform a method, the method comprising:

obtaining, by an n-bit accelerator, multiple input operands packed together as a packed integer, the packed integer being an n-bit integer comprising multiple slots, where input operands of the multiple input operands are packed into every other slot of the multiple slots, with a gap slot being between adjacent input operands of the multiple input operands to avoid corruption between the adjacent input operands, and each slot of the multiple slots has a bitwidth k; and

performing, by the n-bit accelerator, one or more predefined operations using the packed integer, to transform the packed integer into result data which facilitates cryptographic-related processing, wherein the performing comprises:

performing, by the n-bit accelerator, an arithmetic operation of the one or more predefined operations, the performing using the input operands packed in the packed integer to obtain an intermediate result integer comprising multiple low-part and high-part result components in different slots of the intermediate result integer; and

repacking the multiple low-part and high-part result components of the intermediate result integer into a low-part packed integer and a separate high-part packed integer to facilitate obtaining the result data.

2. The computer system of claim 1 , wherein the repacking further comprises:

shuffling and repacking the intermediate result integer to obtain the low-part packed integer and the high-part packed integer, the low-part packed integer being a respective n-bit integer comprising multiple slots, where low-order parts of the intermediate result are packed into every other slot of the multiple slots, with each low-order part being k-bits wide, starting from a least-significant bit of a respective result component of the intermediate result, and the high-part packed integer being a respective n-bit integer comprising multiple slots, where high-order parts of the intermediate result are packed into every other slot of the multiple slots, with each high-order part being k-bits wide, starting from a most-significant bit of the respective result component of the intermediate result.

3. The computer system of claim 2 , further comprising:

separately using the low-part packed integer and the high-part packed integer in facilitating obtaining the result data which facilitates the cryptographic-related processing.

4. The computer system of claim 2 , further comprising:

performing, by the n-bit accelerator, another arithmetic operation using the high-part packed integer and a predetermined constant u, the predetermined constant u being dependent, in part, on the bitwidth k, where performing the other arithmetic operation generates another intermediate result comprising multiple result components;

shuffling and repacking the other intermediate result to obtain another high-part packed integer, the other high-part packed integer being another n-bit integer comprising multiple slots, where high-order parts of the multiple result components of the other intermediate result are packed into every other slot of the multiple slots; and

using the other high-part packed integer in facilitating obtaining the result data which facilitates the cryptographic-related processing.

5. The computer system of claim 4 , wherein the using the other high-part packed integer further comprises:

performing a further arithmetic operation using the other high-part packed integer and a predefined prime value to obtain a further intermediate result comprising multiple result components; and

shuffling and repacking the further intermediate result to obtain a further low-part packed integer, the further low-part packed integer being a further n-bit integer comprising multiple slots, where low-order parts of the multiple result components of the further intermediate result are packed into every other slot of the multiple slots; and

using the further low-part packed integer in facilitating obtaining the result data which facilitates the cryptographic-related processing.

6. The computer system of claim 2 , further comprising performing one or more correction operations using, at least in part, the low-part packed integer to obtain the result data.

7. The computer system of claim 1 , wherein the packed integer further comprises a null value of bitwidth kin the gap slot of the multiple slots located between two adjacent input operands of the multiple input operands packed into every other slot of the multiple slots.

8. The computer system of claim 1 , wherein the result data facilitates lattice-based cryptographic processing, and the n-bit accelerator comprises a modular arithmetic, hardware accelerator unit.

9. The computer system of claim 1 , wherein the bitwidth k of the multiple slots comprises one of 16-bits or 32-bits.

10. A computer-implemented method of facilitating cryptographic-related processing within a computing environment, the computer-implemented method comprising:

obtaining, by an n-bit accelerator, multiple input operands packed together as a packed integer, the packed integer being an n-bit integer comprising multiple slots, where input operands of the multiple input operands are packed into every other slot of the multiple slots, with a gap slot being between adjacent input operands of the multiple input operands to avoid corruption between the adjacent input operands, and each slot of the multiple slots has a bitwidth k; and

performing, by the n-bit accelerator, one or more predefined operations using the packed integer, to transform the packed integer into result data which facilitates cryptographic-related processing, wherein the performing comprises:

performing, by the n-bit accelerator, an arithmetic operation of the one or more predefined operations, the performing using the input operands packed in the packed integer to obtain an intermediate result integer comprising multiple low-part and high-part result components in different slots of the intermediate result integer; and

repacking the multiple low-part and high-part result components of the intermediate result integer into a low-part packed integer and a separate high-part packed integer to facilitate obtaining the result data.

11. The computer-implemented method of claim 10 , wherein the repacking further comprises:

shuffling and repacking the intermediate result integer to obtain the low-part packed integer and the high-part packed integer, the low-part packed integer being a respective n-bit integer comprising multiple slots, where low-order parts of the intermediate result are packed into every other slot of the multiple slots, with each low-order part being k-bits wide, starting from a least-significant bit of a respective result component of the intermediate result, and the high-part packed integer being a respective n-bit integer comprising multiple slots, where high-order parts of the intermediate result are packed into every other slot of the multiple slots, with each high-order part being k-bits wide, starting from a most-significant bit of the respective result component of the intermediate result; and

separately using the low-part packed integer and the high-part packed integer in facilitating obtaining the result data which facilitates the cryptographic-related processing.

12. The computer-implemented method of claim 11 , further comprising:

performing, by the n-bit accelerator, another arithmetic operation using the high-part packed integer and a predetermined constant u, the predetermined constant u being dependent, in part, on the bitwidth k, where performing the other arithmetic operation generates another intermediate result comprising multiple result components;

shuffling and repacking the other intermediate result to obtain another high-part packed integer, the other high-part packed integer being another n-bit integer comprising multiple slots, where high-order parts of the multiple result components of the other intermediate result are packed into every other slot of the multiple slots; and

using the other high-part packed integer in facilitating obtaining the result data which facilitates the cryptographic-related processing.

13. The computer-implemented method of claim 12 , wherein the using the other high-part packed integer further comprises:

performing a further arithmetic operation using the other high-part packed integer and a predefined prime value to obtain a further intermediate result comprising multiple result components; and

shuffling and repacking the further intermediate result to obtain a further low-part packed integer, the further low-part packed integer being a further n-bit integer comprising multiple slots, where low-order parts of the multiple result components of the further intermediate result are packed into every other slot of the multiple slots; and

using the further low-part packed integer in facilitating obtaining the result data which facilitates the cryptographic-related processing.

14. The computer-implemented method of claim 11 , further comprising performing one or more correction operations using, at least in part, the low-part packed integer to obtain the result data.

15. The computer-implemented method of claim 10 , wherein the packed integer further comprises a null value of bitwidth kin the gap slot of the multiple slots located between two adjacent input operands of the multiple input operands packed into every other slot of the multiple slots.

16. The computer-implemented method of claim 10 , wherein the result data facilitates lattice-based cryptographic processing, and the n-bit accelerator comprises a modular arithmetic, hardware accelerator unit.

17. The computer-implemented method of claim 10 , wherein the bitwidth k of the multiple slots comprises one of 16-bits or 32-bits.

18. A computer program product for facilitating cryptographic-related processing within a computing environment, the computer program product comprising:

at least one computer-readable storage medium having program instructions embodied therewith, the program instructions being readable by a processing circuit to cause the processing circuit to perform a method comprising:

obtaining, by an n-bit accelerator, multiple input operands packed together as a packed integer, the packed integer being an n-bit integer comprising multiple slots, where input operands of the multiple input operands are packed into every other slot of the multiple slots, with a gap slot being between adjacent input operands of the multiple input operands to avoid corruption between the adjacent input operands, and each slot of the multiple slots has a bitwidth k; and

performing, by the an n-bit accelerator, one or more predefined operations using the packed integer, to transform the packed integer into result data which facilitates cryptographic-related processing, wherein the performing comprises:

performing, by the n-bit accelerator, an arithmetic operation of the one or more predefined operations, the performing using the input operands packed in the packed integer to obtain an intermediate result integer comprising multiple low-part and high-part result components in different slots of the intermediate result integer; and

repacking the multiple low-part and high-part result components of the intermediate result integer into a low-part packed integer and a separate high-part packed integer to facilitate obtaining the result data.

19. The computer program product of claim 18 , wherein the repacking further comprises:

shuffling and repacking the intermediate result integer to obtain the low-part packed integer and the high-part packed integer, the low-part packed integer being a respective n-bit integer comprising multiple slots, where low-order parts of the intermediate result are packed into every other slot of the multiple slots, with each low-order part being k-bits wide, starting from a least-significant bit of a respective result component of the intermediate result, and the high-part packed integer being a respective n-bit integer comprising multiple slots, where high-order parts of the intermediate result are packed into every other slot of the multiple slots, with each high-order part being k-bits wide, starting from a most-significant bit of the respective result component of the intermediate result.

20. The computer program product of claim 19 , further comprising:

performing, by the n-bit accelerator, another arithmetic operation using the high-part packed integer and a predetermined constant u, the predetermined constant u being dependent, in part, on the bitwidth k, where performing the other arithmetic operation generates another intermediate result comprising multiple result components;

shuffling and repacking the other intermediate result to obtain another high-part packed integer, the other high-part packed integer being another n-bit integer comprising multiple slots, where high-order parts of the multiple result components of the other intermediate result are packed into every other slot of the multiple slots; and

using the other high-part packed integer in facilitating obtaining the result data which facilitates the cryptographic-related processing.