Generation of dynamic design flows for integrated circuits
Systems and methods are disclosed for to generation of dynamic design flows for integrated circuits. For example, a method may include accessing a design flow configuration data structure, wherein the design flow configuration data structure is encoded in a tool control language; based on the design flow configuration data structure, selecting multiple flowmodules from a set of flowmodules, wherein each flowmodule provides an application programming interface, in the tool control language, to a respective electronic design automation tool; based on the design flow configuration data structure, generating a design flow as a directed acyclic graph including the selected flowmodules as vertices; and generating an output integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the design flow to control the respective electronic design automation tools of the selected flowmodules.
1. A method comprising:
based on a design flow configuration data structure, generating a design flow as a directed acyclic graph including flowmodules as vertices, wherein a flowmodule in the design flow provides an application programming interface to an electronic design automation tool; and
generating an output integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the design flow to control the electronic design automation tool.
2. The method of claim 1 , in which generating the design flow comprises:
generating, based on the design flow configuration data structure, a first design flow;
generating a current integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the first design flow;
determining one or more parameters of the current integrated circuit design data structure;
inputting the one or more parameters to a machine learning module to obtain one or more feedback parameters as output of the machine learning module; and
generating, based on the one or more feedback parameters, a next design flow.
3. The method of claim 2 , wherein the one or more parameters of the current integrated circuit design data structure include estimates of power, performance, and area for an integrated circuit described by the current integrated circuit design data structure.
4. The method of claim 1 , comprising:
generating a graphical representation of the directed acyclic graph of the design flow; and
transmitting, storing, or displaying the graphical representation.
5. The method of claim 1 , wherein the design flow includes a vertex corresponding to a task for hypertext markup language generation, comprising:
generating a hypertext markup language data structure, based on the output integrated circuit design data structure, using the design flow; and
transmitting, storing, or displaying the hypertext markup language data structure.
6. The method of claim 1 , wherein the design flow configuration data structure is part of a design parameters data structure, comprising:
accessing the design parameters data structure, wherein the design parameters data structure includes values of design parameters of an integrated circuit design;
responsive to a command identifying the design parameters data structure, generating a register-transfer level data structure for an integrated circuit based on the design parameters data structure;
responsive to the command identifying the design parameters data structure, generating a software development kit for the integrated circuit based on the register-transfer level data structure;
wherein the design flow is generated responsive to the command identifying the design parameters data structure;
wherein the output integrated circuit design data structure includes a physical design data structure for the integrated circuit that is generated, responsive to the command identifying the design parameters data structure, based on the register-transfer level data structure;
responsive to the command identifying the design parameters data structure, generating a test plan for the integrated circuit based on the design parameters data structure and acceptance criteria;
responsive to the command identifying the design parameters data structure, invoking tests for the integrated circuit based on the test plan, the register-transfer level data structure, the software development kit, and the physical design data structure to obtain a set of test results; and
transmitting, storing, or displaying a design data structure based on the register-transfer level data structure, the software development kit, the physical design data structure, and the test results.
7. The method of claim 1 , comprising:
based on the design flow configuration data structure, selecting multiple flowmodules from a set of flowmodules, wherein the design flow is generated to include the selected flow modules as vertices in the directed acyclic graph.
8. A system comprising:
a memory; and
a processor, wherein the memory includes instructions executable by the processor to cause the system to:
based on a design flow configuration data structure, generate a design flow as a directed acyclic graph including flowmodules as vertices, wherein a flowmodule in the design flow provides an application programming interface to an electronic design automation tool; and
generate an output integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the design flow to control the electronic design automation tool.
9. The system of claim 8 , wherein the memory includes instructions executable by the processor to cause the system to:
generate, based on the design flow configuration data structure, a first design flow;
generate a current integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the first design flow;
determine one or more parameters of the current integrated circuit design data structure;
input the one or more parameters to a machine learning module to obtain one or more feedback parameters as output of the machine learning module; and
generate, based on the one or more feedback parameters, a next design flow.
10. The system of claim 9 , wherein the one or more parameters of the current integrated circuit design data structure include estimates of power, performance, and area for an integrated circuit described by the current integrated circuit design data structure.
11. The system of claim 8 , wherein the memory includes instructions executable by the processor to cause the system to:
generate a graphical representation of the directed acyclic graph of the design flow; and
transmit, store, or display the graphical representation.
12. The system of claim 8 , wherein the design flow configuration data structure is part of a design parameters data structure, and the memory includes instructions executable by the processor to cause the system to:
access the design parameters data structure, wherein the design parameters data structure includes values of design parameters of an integrated circuit design;
responsive to a command identifying the design parameters data structure, generate a register-transfer level data structure for an integrated circuit based on the design parameters data structure;
responsive to the command identifying the design parameters data structure, generate a software development kit for the integrated circuit based on the register-transfer level data structure;
wherein the design flow is generated responsive to the command identifying the design parameters data structure;
wherein the output integrated circuit design data structure includes a physical design data structure for the integrated circuit that is generated, responsive to the command identifying the design parameters data structure, based on the register-transfer level data structure;
responsive to the command identifying the design parameters data structure, generate a test plan for the integrated circuit based on the design parameters data structure and acceptance criteria; and
responsive to the command identifying the design parameters data structure, invoke tests for the integrated circuit based on the test plan, the register-transfer level data structure, the software development kit, and the physical design data structure to obtain a set of test results.
13. The system of claim 8 , wherein the memory includes instructions executable by the processor to cause the system to:
based on the design flow configuration data structure, select multiple flowmodules from a set of flowmodules, wherein the design flow is generated to include the selected flow modules as vertices in the directed acyclic graph.
14. A non-transitory computer-readable storage medium that includes instructions that, when executed by a processor, facilitate performance of operations comprising:
based on a design flow configuration data structure, generating a design flow as a directed acyclic graph including flowmodules as vertices, wherein a flowmodule in the design flow provides an application programming interface to an electronic design automation tool; and
generating an output integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the design flow to control the electronic design automation tool.
15. The non-transitory computer-readable storage medium of claim 14 , in which generating the design flow comprises:
generating, based on the design flow configuration data structure, a first design flow;
generating a current integrated circuit design data structure, based on one or more input integrated circuit design data structures, using the first design flow;
determining one or more parameters of the current integrated circuit design data structure;
inputting the one or more parameters to a machine learning module to obtain one or more feedback parameters as output of the machine learning module; and
generating, based on the one or more feedback parameters, a next design flow.
16. The non-transitory computer-readable storage medium of claim 15 , wherein the one or more parameters of the current integrated circuit design data structure include estimates of power, performance, and area for an integrated circuit described by the current integrated circuit design data structure.
17. The non-transitory computer-readable storage medium of claim 14 , that includes instructions that, when executed by a processor, facilitate performance of operations comprising:
generating a graphical representation of the directed acyclic graph of the design flow; and transmitting, storing, or displaying the graphical representation.
18. The non-transitory computer-readable storage medium of claim 14 , wherein the design flow includes a vertex corresponding to a task for hypertext markup language generation, that includes instructions that, when executed by a processor, facilitate performance of operations comprising:
generating a hypertext markup language data structure, based on the output integrated circuit design data structure, using the design flow; and
transmitting, storing, or displaying the hypertext markup language data structure.
19. The non-transitory computer-readable storage medium of claim 14 , wherein the design flow configuration data structure is part of a design parameters data structure, that includes instructions that, when executed by a processor, facilitate performance of operations comprising:
accessing the design parameters data structure, wherein the design parameters data structure includes values of design parameters of an integrated circuit design;
responsive to a command identifying the design parameters data structure, generating a register-transfer level data structure for an integrated circuit based on the design parameters data structure;
responsive to the command identifying the design parameters data structure, generating a software development kit for the integrated circuit based on the register-transfer level data structure;
wherein the output integrated circuit design data structure includes a physical design data structure for the integrated circuit that is generated, responsive to the command identifying the design parameters data structure, based on the register-transfer level data structure;
responsive to the command identifying the design parameters data structure, generating a test plan for the integrated circuit based on the design parameters data structure and acceptance criteria;
responsive to the command identifying the design parameters data structure, invoking tests for the integrated circuit based on the test plan, the register-transfer level data structure, the software development kit, and the physical design data structure to obtain a set of test results; and
transmitting, storing, or displaying a design data structure based on the register-transfer level data structure, the software development kit, the physical design data structure, and the test results.
20. The non-transitory computer-readable storage medium of claim 14 , that includes instructions that, when executed by a processor, facilitate performance of operations comprising:
based on the design flow configuration data structure, selecting multiple flowmodules from a set of flowmodules, wherein the design flow is generated to include the selected flow modules as vertices in the directed acyclic graph.