Scan driving circuit and display device including the same
A scan driving circuit includes: a driving circuit configured to output a scan signal to an output terminal in response to clock signals and a carry signal; and a masking circuit configured to stop the driving circuit from outputting the scan signal in response to a masking signal and a signal indicating an operating state of the driving circuit.
1. A scan driving circuit comprising:
a driving circuit configured to transmit a carry signal to a first node in response to a clock signal, and to output a scan signal to an output terminal in response to the clock signal and the carry signal of the first node; and
a masking circuit electrically connected between the first node and a first voltage terminal,
wherein the masking circuit comprises:
a first masking transistor configured to electrically connect the first node and a masking node in response to a masking signal; and
a second masking transistor configured to electrically connect the masking node and the first voltage terminal in response to a signal indicating an operating state of the driving circuit.
2. The scan driving circuit of claim 1 , wherein the driving circuit comprises:
a first transistor configured to transmit the carry signal to the first node in response to the clock signal; and
a second transistor configured to connect the output terminal to the first voltage terminal in response to the carry signal of the first node.
3. The scan driving circuit of claim 2 , wherein the first voltage terminal is configured to receive a first voltage.
4. The scan driving circuit of claim 2 , wherein the driving circuit further comprises:
a third transistor connected between a second voltage terminal configured to receive a second voltage and the output terminal and comprising a gate electrode connected to a second node; and
a fourth transistor connected between the second voltage terminal and the second node and comprising a gate electrode connected to the first node.
5. The scan driving circuit of claim 1 , wherein the signal indicating the operating state of the driving circuit is the carry signal or the scan signal.
6. The scan driving circuit of claim 1 , wherein the second masking transistor is electrically connected between the masking node and the first voltage terminal and comprises a gate electrode connected to the output terminal configured to receive the scan signal.
7. The scan driving circuit of claim 1 , wherein the second masking transistor is electrically connected between the masking node and the first voltage terminal and comprises a gate electrode connected to an input terminal configured to receive the carry signal.
8. The scan driving circuit of claim 1 , wherein the second masking transistor is electrically connected between the masking node and the first voltage terminal and comprises a gate electrode connected to the first node.
9. A scan driving circuit comprising:
a driving circuit configured to output a scan signal in response to a clock signal and a carry signal; and
a masking circuit electrically connected to an input terminal configured to receive the carry signal and a first voltage terminal,
wherein the masking circuit comprises:
a first masking switch configured to electrically connect the first voltage terminal and a connection node in response to the scan signal; and
a second masking switch configured to electrically connect the input terminal and the connection node in response to a masking signal.
10. The scan driving circuit of claim 9 , wherein the second masking switch is configured to electrically disconnect the input terminal and the connection node when the masking signal has a first level.
11. A display device comprising:
a display panel comprising a plurality of scan lines;
a scan driving circuit configured to drive the plurality of scan lines; and
a driving controller configured to control the scan driving circuit,
wherein the scan driving circuit comprises a plurality of driving stages, each of the plurality of driving stages being configured to drive a corresponding scan line from among the plurality of scan lines,
wherein each of the plurality of driving stages comprises:
a driving circuit configured to transmits a carry signal to a first node in response to a clock signal, and to output a scan signal to an output terminal in response to the clock signal and the carry signal of the first node; and
a masking circuit electrically connected between the first node and a first voltage terminal,
wherein the masking circuit comprises:
a first masking transistor configured to electrically connect the first node and a masking node in response to a masking signal; and
a second masking transistor configured to electrically connect the masking node and the first voltage terminal in response to a signal indicating an operating state of the driving circuit.
12. The display device of claim 11 , wherein the display panel comprises a first area and a second area, and
the masking signal indicates a scan line corresponding to a start point of the second area from among the plurality of scan lines.
13. The display device of claim 11 , wherein the driving circuit comprises:
a first transistor configured to transmit the carry signal to the first node in response to the clock signal; and
a second transistor configured to connect the output terminal to the first voltage terminal in response to the carry signal of the first node.
14. The display device of claim 13 , wherein the first voltage terminal is configured to receive a first voltage.
15. The display device of claim 13 , wherein the driving circuit further comprises:
a third transistor connected between a second voltage terminal configured to receive a second voltage and the output terminal and comprising a gate electrode connected to a second node; and
a fourth transistor connected between the second voltage terminal and the second node and comprising a gate electrode connected to the first node.
16. The display device of claim 11 , wherein the signal indicating the operating state of the driving circuit is the carry signal or the scan signal.
17. The display device of claim 11 , wherein the second masking transistor is electrically connected between the masking node and a first voltage terminal and comprises a gate electrode connected to the output terminal configured to receive the scan signal.
18. The display device of claim 11 , wherein the second masking transistor is electrically connected between the masking node and a first voltage terminal and comprises a gate electrode connected to an input terminal configured to receive the carry signal.
19. The display device of claim 11 , wherein the second masking transistor is electrically connected between the masking node and a first voltage terminal and comprises a gate electrode connected to the first node.