Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor device includes a semiconductor substrate, a first gate structure over the substrate, a second gate structure over the substrate, first gate spacers, second gate spacers, first and second metal layers spanning over the first and second gate structures, first and second contact plugs extending through the first and second metal layers, respectively. The first gate structure includes a first gate dielectric, and a first work function metal layer over the first gate dielectric. The second gate structure is wider than the first gate structure, wherein the second gate structure includes a second gate dielectric, a second work function metal layer over the second gate dielectric, and a filling conductor over the second work function metal layer. The first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor.
1. A semiconductor device, comprising:
a substrate;
a first gate structure over the substrate, wherein the first gate structure comprises:
a first gate dielectric; and
a first work function metal layer over the first gate dielectric;
a second gate structure over the substrate, the second gate structure being wider than the first gate structure, wherein the second gate structure comprises:
a second gate dielectric;
a second work function metal layer over the second gate dielectric; and
a filling conductor over the second work function metal layer;
first gate spacers on opposite sidewalls of the first gate structure;
second gate spacers on opposite sidewalls of the second gate structure;
first and second metal layers spanning over the first and second gate structures, respectively; and
first and second contact plugs extending through the first and second metal layers, respectively, wherein the first contact plug is in contact with the first work function metal layer, and the second contact plug is in contact with the filling conductor.
2. The semiconductor device of claim 1 , wherein top surfaces of the first and second metal layers are lower than top surfaces of the first and second gate spacers.
3. The semiconductor device of claim 1 , wherein the first metal layer is in contact with the first gate dielectric and the first work function metal layer, and the second metal layer is in contact with the second gate dielectric, the second work function metal layer, and the filling conductor.
4. The semiconductor device of claim 1 , wherein the first and second metal layers have a bar-shape cross-section, while the first gate dielectric, the first work function metal layer, the second gate dielectric and the second work function metal layer have a U-shape cross-section.
5. The semiconductor device of claim 1 , further comprising first and second protective layers over the first and second metal layers, respectively, the first protective layer being laterally between the first gate spacers, and the second protective layer being laterally between the second gate spacers.
6. The semiconductor device of claim 5 , further comprising first and second liners lining the first and second protective layers, respectively.
7. The semiconductor device of claim 6 , wherein the first protective layer and the first liner are in contact with the first contact plug, and the second protective layer and the second liner are in contact with the second contact plug.
8. The semiconductor device of claim 1 , wherein the second gate structure has more layers than the first gate structure.
9. The semiconductor device of claim 1 , wherein the first gate structure is free of a material of the filling conductor of the second gate structure.
10. A semiconductor device, comprising:
a substrate;
a first gate structure over the substrate, wherein the first gate structure comprises:
a first gate dielectric; and
a first work function metal layer over the first gate dielectric, wherein a topmost end of the first gate dielectric is higher than a topmost end of the first work function metal layer;
a second gate structure over the substrate, wherein the second gate structure comprises:
a second gate dielectric;
a second work function metal layer over the second gate dielectric; and
a filling conductor over the second work function metal layer;
first gate spacers on opposite sidewalls of the first gate structure;
second gate spacers on opposite sidewalls of the second gate structure;
a first metal layer over and in contact with the first gate structure; and
a second metal layer over and in contact with the second gate structure, wherein the second metal layer has a top surface level with a top surface of the first metal layer, and a bottom surface higher than a bottom surface of the first metal layer, and wherein the bottom surface of the first metal layer is flatter than the bottom surface of the second metal layer.
11. The semiconductor device of claim 10 , wherein the bottom surface of the second metal layer is curved.
12. The semiconductor device of claim 10 , wherein the first metal layer is in contact with the first gate dielectric and the second metal layer is separated from the second gate dielectric.
13. The semiconductor device of claim 10 , wherein a topmost end of the first work function metal layer is lower than a topmost end of the second work function metal layer.
14. The semiconductor device of claim 10 , wherein the second gate structure is wider than the first gate structure.
15. The semiconductor device of claim 10 , wherein the first gate structure is free of a material of the filling conductor of the second gate structure.
16. A semiconductor device, comprising:
a substrate;
a first gate structure over the substrate, wherein the first gate structure comprises:
a first gate dielectric; and
a first work function metal (WFM) layer over the first gate dielectric; and
a second gate structure over the substrate, wherein the second gate structure comprises:
a second gate dielectric;
a second WFM layer over the second gate dielectric; and
a filling metal over the second WFM layer;
first gate spacers on opposite sidewalls of the first gate structure;
second gate spacers on opposite sidewalls of the second gate structures;
first and second tungsten layers spanning over the first and second gate structures, respectively; and
first and second contact plugs extending through the first and second tungsten layers, respectively, wherein the first contact plug is in contact with the first WFM layer, and the second contact plug is in contact with the filling metal.
17. The semiconductor device of claim 16 , wherein the first tungsten layer is in contact with the first gate spacers.
18. The semiconductor device of claim 17 , wherein the second tungsten layer is in contact with the second gate spacers.
19. The semiconductor device of claim 16 , wherein the first and second tungsten layers both comprise a bar-shape cross-sectional.
20. The semiconductor device of claim 19 , wherein the first gate dielectric, the first WFM layer, the second gate dielectric, and the second WFM layer have a U-shaped cross-section.