Semiconductor device

1. An apparatus, comprising:

a memory mat including a plurality of vertical memory cell transistors;

a shield structure surrounding each of the plurality of vertical memory cell transistors, the shield structure comprising a conductive material; and

a ring-shaped wiring above the shield structure, the ring-shaped wiring being connected to the shield structure in an edge region of the shield structure.

2. The apparatus of claim 1 , further comprising at least one power wiring above the ring-shaped wiring, the at least power wiring being connected to the ring- shaped wiring in a corner region of the ring-shaped wiring.

3. The apparatus of claim 1 , wherein the shield structure comprises a main surface portion surrounding top portions of channels of the plurality of vertical memory cell transistors.

4. The apparatus of claim 3 , wherein the shield structure further comprises vertically extending portions each formed adjacently to a corresponding one of gates of the plurality of vertical memory cell transistors.

5. The apparatus of claim 1 , further comprising a plurality of memory cell capacitors, each of the plurality of memory cell capacitors being on a corresponding one of top portions of channels of the plurality of vertical memory cell transistors.

6. The apparatus of claim 1 , wherein the shield structure comprises silicon doped with phosphorus or arsenic as an impurity.

7. An apparatus,. comprising:

a semiconductor substrate;

a memory mat region on the semiconductor substrate;

a plurality of channel pillars arranged in the memory mat region and arranged so as to extend in a direction perpendicular to an upper surface of the semiconductor substrate;

a plurality of peripheral pillars surrounding an outermost periphery of the memory mat region;

a shield structure arranged between the plurality of channel pillars and the plurality of peripheral pillars, the shield structure having a first portion surrounding each of the plurality of channel pillars and a second portion surrounding each of the plurality of peripheral pillars, the shield structure comprising a conductive material; and

an extraction electrode electrically connected to the shield structure.

8. The apparatus of claim 7 , further comprising:

a plurality of storage capacitors, each of the plurality of storage capacitors being connected to one side of a corresponding one of the plurality of channel pillars; and

a plurality of bit lines, each of the plurality of bit lines being connected to another side of the corresponding one of the plurality of channel pillars.

9. The apparatus of claim 7 , further comprising a landing pad arranged between the second portion of the shield structure and the extraction electrode, the landing pad being connected to the second portion of the shield structure and the extraction electrode.

10. The apparatus of claim 9 , wherein the landing pad is provided so as to surround the memory mat region.

11. The apparatus of claim 7 , wherein the shield structure comprises silicon doped with phosphorus or arsenic as an impurity.

12. The apparatus of claim 7 , wherein the extraction electrode comprises titanium nitride.

13. An apparatus, comprising:

a semiconductor substrate;

a memory mat arranged on the semiconductor substrate and having a rectangular shape,

a plurality of storage capacitors arranged in the memory mat;

a plurality of dummy capacitors arranged to surround the plurality of storage capacitors; and

a landing pad surrounding the plurality of storage capacitors;

wherein the plurality of dummy capacitors are located above the landing pad,

wherein the apparatus further comprises:

a plurality of channel pillars arranged in the memory mat, each of the plurality of channel pillars being electrically connected to a corresponding one of the plurality of storage capacitors;

a plurality of peripheral pillars surrounding the plurality of channel pillars; and

a shield structure surrounding each of the plurality of channel pillars and each of the plurality of peripheral pillars in a mesh pattern, the shield structure comprising a conductive material.

14. The apparatus of claim 13 , further comprising:

wherein the shield structure comprises a center shield structure arranged in a center region of the shield structure and a peripheral shield structure surrounding the center shield structure; and

wherein the landing pad is electrically connected to the plurality of dummy capacitors, the plurality of peripheral pillars, and the peripheral shield structure.

15. The apparatus of claim 14 , wherein the landing pad is arranged between the plurality of dummy capacitors and the peripheral shield structure.

16. The apparatus of claim 14 , wherein each of the plurality of channel pillars and each of the plurality of storage capacitors corresponding to each other are stacked in a direction perpendicular to an upper surface of the semiconductor substrate.

17. The apparatus of claim 14 , further comprising a lower pad and a pedestal on the lower pad, wherein both the lower pad and the pedestal are between the corresponding one of the plurality of storage capacitors and a corresponding one of the plurality of channel pillars;

wherein the landing pad comprises a lower landing pad and an upper landing pad on the lower landing pad; and

wherein the lower landing pad and the lower pad comprise a same material, and the upper landing pad and the pedestal comprise a same material.

18. The apparatus of claim 14 , wherein the shield structure comprises silicon doped with phosphorus or arsenic as an impurity.