Load adjusted populations of integrated circuit decoupling capacitors

1. A method, comprising:

iterating application of a load profile across different populations of decoupling capacitors on a circuit board for supply voltage domains of an integrated circuit device until a target transient performance is reached for the supply voltage domains, wherein the load profile is applied onto electrical connections corresponding to the supply voltage domains for a footprint of the integrated circuit device while the integrated circuit device is not populated onto the circuit board; and

generating a capacitor population configuration for the circuit board based on a population of the decoupling capacitors that achieves the target transient performance.

2. The method of claim 1 , further comprising:

for each iteration, determining if margin exists in the transient performance to support removal of one or more decoupling capacitors and employing a population configuration comprising removal of the one or more capacitors during a subsequent iteration.

3. The method of claim 2 , further comprising:

selecting the one or more decoupling capacitors as being electrically furthest from the electrical connections among a present population of decoupling capacitors.

4. The method of claim 2 , wherein determining if the margin exists in the transient performance comprises comparing the transient performance to a target specification of margin for transient performance of the integrated circuit device.

5. The method of claim 4 , wherein the target specification of margin comprises a manufacturer supplied margin for the integrated circuit device with an end-of-life guardband applied to the manufacturer supplied margin.

6. The method of claim 1 , further comprising:

controlling assembly of capacitors onto a target circuit board in accordance with the capacitor population configuration.

7. The method of claim 6 , further comprising:

operating the target circuit board having a corresponding integrated circuit device populated thereon;

monitoring transient performance for the supply voltage domains during operation of the corresponding integrated circuit device;

verifying the transient performance for the supply voltage domains is in accordance with the target transient performance.

8. The method of claim 1 , wherein the target transient performance comprises performance of voltage transient levels monitored for the supply voltage domains during application of the load profile.

9. The method of claim 1 , wherein the footprint is for a carrier assembly for a semiconductor die comprising the integrated circuit device;

wherein the carrier assembly is attached to the circuit board without the semiconductor die coupled thereto; and

wherein the load profile is applied to electrical connections on the carrier assembly for the semiconductor die.

10. The method of claim 1 , wherein the load profile is based in part on reduced operating voltages for the supply voltage domains determined from executing a performance test on a representative integrated circuit device to determine the reduced operating voltages as lower than a manufacturer specified voltage level for the supply voltage domains.

11. An apparatus, comprising:

one or more computer readable storage media;

program instructions stored on the one or more computer readable storage media, the program instructions executable by a processing system to direct the processing system to at least:

iterate application of a load profile across different populations of decoupling capacitors on a circuit board for supply voltage domains of an integrated circuit device until a target transient performance is reached for the supply voltage domains, wherein the load profile is applied onto electrical connections corresponding to the supply voltage domains for a footprint of the integrated circuit device while the integrated circuit device is not populated onto the circuit board; and

generate a capacitor population configuration for the circuit board based on a population of the decoupling capacitors that achieves the target transient performance.

12. The apparatus of claim 11 , comprising further instructions executable by the processing system to direct the processing system to at least:

for each iteration, determine if margin exists in the transient performance to support removal of one or more decoupling capacitors and produce a population configuration comprising removal of the one or more capacitors during a subsequent iteration.

13. The apparatus of claim 12 , comprising further instructions executable by the processing system to direct the processing system to at least:

select the one or more decoupling capacitors as being electrically furthest from the electrical connections among a present population of decoupling capacitors.

14. The apparatus of claim 12 , comprising further instructions executable by the processing system to direct the processing system to at least:

determine if the margin exists in the transient performance by at least comparing the transient performance to a target specification of margin for transient performance of the integrated circuit device.

15. The apparatus of claim 14 , wherein the target specification of margin comprises a manufacturer supplied margin for the integrated circuit device with an end-of-life guardband applied to the manufacturer supplied margin.

16. The apparatus of claim 11 , comprising further instructions executable by the processing system to direct the processing system to at least:

control assembly of capacitors onto a target circuit board in accordance with the capacitor population configuration.

17. The apparatus of claim 16 , comprising further instructions executable by the processing system to direct the processing system to at least:

operate the target circuit board having a corresponding integrated circuit device populated thereon;

monitor transient performance for the supply voltage domains during operation of the corresponding integrated circuit device;

verify the transient performance for the supply voltage domains is in accordance with the target transient performance.

18. A control system, comprising:

across an iteratively reduced population of decoupling capacitors, a test interface configured to instruct a test fixture to apply a load profile onto electrical connections of a circuit board corresponding to supply voltage domains for a footprint of an integrated circuit device while the integrated circuit device is not populated onto the circuit board;

a test profiler configured to monitor transient performance of the supply voltage domains and determine when a target transient performance is reached for the supply voltage domains;

the test profiler configured to generate a capacitor population configuration for the circuit board based on a population of the decoupling capacitors that achieves the target transient performance.

19. The control system of claim 18 , comprising:

the test profiler configured to select one or more decoupling capacitors for removal before performance of a subsequent iteration; and

the test profiler configured to transfer an indication of the selection of the one or more decoupling capacitors;

wherein the one or more capacitors are selected as being electrically furthest from the electrical connections among a present population of decoupling capacitors.