IP Library › Granted Patent US 11,923,205
Granted Patent B2
US 11,923,205 · App. 17/553,851 · Granted Mar 5, 2024

Method for manufacturing semiconductor device

Inventors: Kun-Ju Li (Tainan, TW); Ang Chan (Taipei, TW); Hsin-Jung Liu (Pingtung County, TW); Wei-Xin Gao (Tainan, TW); Jhih-Yuan Chen (Kaohsiung, TW); Chun-Han Chen (Hsinchu, TW); Zong-Sian Wu (Tainan, TW); Chau-Chung Hou (Tainan, TW); I-Ming Lai (Tainan, TW); Fu-Shou Tsai (Kaohsiung, TW)
Assignee: UNITED MICROELECTRONICS CORPORATION
H01L21/47H01L21/76237H01L21/76251
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Quick Facts
Patent No.
US 11,923,205
App. No.
17/553,851
Granted
Mar 5, 2024
Kind
B2
Abstract

A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.

Claims (20)

1. A method for manufacturing a semiconductor device, comprising:

providing a wafer-bonding stack structure comprising a sidewall layer and an exposed first component layer;

forming a photoresist layer on the first component layer;

performing an edge trimming process to at least remove the sidewall layer; and

removing the photoresist layer,

wherein a method for manufacturing the wafer-bonding stack structure comprises:

providing a first wafer structure and a second wafer structure, wherein the first wafer structure comprises a first substrate and the first component layer formed on the first substrate, and the second wafer structure comprises a second substrate and a second component layer formed on the second substrate;

bonding the first wafer structure and the second wafer structure, wherein the first component layer and the second component layer face each other, and at least one interconnection layer is used to bond the first component layer and the second component layer;

performing a thinning process to thin the first substrate;

trimming the periphery of the stacked thinned first substrate, first component layer, interconnection layer, second component layer, to obtain a trimmed peripheral wall;

depositing a protective layer to at least cover the thinned first substrate and the trimming peripheral wall, wherein the protective layer comprises a top layer and the sidewall layer, the top layer is arranged on the thinned first substrate, and the sidewall layer is arranged around the trimming peripheral wall; and

removing the top layer and the thinned first substrate to expose the first component layer.

2. The method for manufacturing the semiconductor device according to claim 1 , wherein the interconnection layer comprises a solder bonding structure, a metal-to-metal direct bonding structure, or a hybrid bonding structure.

3. The method for manufacturing the semiconductor device according to claim 1 , wherein the protective layer is a dielectric layer.

4. The method for manufacturing the semiconductor device according to claim 1 , wherein steps of removing the top layer and the thinned first substrate comprise:

performing a planarizing process to remove the top layer, a portion of the thinned first substrate and a portion of the sidewall layer; and

performing an etching process to remove the remaining thinned first substrate.

5. The method for manufacturing the semiconductor device according to claim 4 , wherein the etching process is a wet etching process.

6. The method for manufacturing the semiconductor device according to claim 1 , wherein a top edge of the sidewall layer is higher than an exposed surface of the first component layer.

7. The method for manufacturing the semiconductor device according to claim 6 , wherein the photoresist layer covers the exposed surface and the top edge of the sidewall layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2021
From: LI, KUN-JU; CHAN, ANG; LIU, HSIN-JUNG; GAO, WEI-XIN; CHEN, JHIH-YUAN; CHEN, CHUN-HAN; WU, ZONG-SIAN; HOU, CHAU-CHUNG; LAI, I-MING; TSAI, FU-SHOU
To: UNITED MICROELECTRONICS CORPORATION
Reel/Frame 058412/0053 →
Continuity (1)
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