Methods of manufacturing semiconductor chip including crack propagation guide
There may be presented a method of manufacturing a semiconductor chip. A first layer stack in which first material layers and second material layers are alternately stacked is formed over a semiconductor substrate including a chip region and a scribe lane region, and first crack propagation guides are formed on the first layer stack. A second layer stack is formed on the first layer stack and the first crack propagation guides, and second crack propagation guides are formed. A semiconductor chip is separated from the semiconductor substrate.
1. A method of manufacturing a semiconductor chip, the method comprising;
forming a first layer stack by alternately stacking first material layers and second material layers over a scribe lane region of a semiconductor substrate, the semiconductor substrate including a chip region and the scribe lane region;
forming trenches that substantially penetrate the first layer stack;
forming first crack propagation guides that fill the trenches;
forming a second layer stack by alternately stacking third material layers and fourth material layers on the first layer stack and the first crack propagation guide;
forming openings substantially penetrating the second layer stack; and
forming second crack propagation guides that fill the opening.
2. The method of claim 1 , further comprising
generating cracks in a portion of the scribe lane region of the semiconductor substrate; and
separating the semiconductor chip with the chip region from the semiconductor substrate by propagating the cracks.
3. The method of claim 2 , wherein the first and second crack propagation guides induce the propagation direction of the cracks to be substantially perpendicular to the semiconductor substrate.
4. The method of claim 2 , wherein the cracks propagate vertically through the first and second crack propagation guides.
5. The method of claim 2 , wherein generating the cracks includes irradiating the portion of the scribe lane region of the semiconductor substrate with a laser.
6. The method of claim 1 , wherein a plurality of second crack propagation guides are overlapped with the first crack propagation guides.
7. The method of claim 1 , wherein the plurality of first crack propagation guides are arranged side by side in the scribe lane region of the semiconductor substrate.
8. The method of claim 1 , wherein the first crack propagation guides include line patterns that are elongated across the scribe lane region of the semiconductor substrate.
9. The method of claim 1 , wherein the opening is formed to expose portions of the first crack propagation guides.
10. The method of claim 1 , wherein each of the openings has a through-hole shape.
11. The method of claim 1 , wherein the first material layer includes silicon oxide, and
wherein the second material layer includes silicon nitride.
12. The method of claim 1 , wherein the third material layer includes silicon oxide, and
wherein the fourth material layer includes silicon nitride.
13. The method of claim 1 , wherein the first and third material layers include the same insulating material,
wherein the second and fourth material layers include the same insulating material, and
wherein the first and second material layers include different insulating materials.
14. The method of claim 1 , wherein each of the first crack propagation guides includes an insulating material.
15. The method of claim 1 , wherein each of the first crack propagation guides includes silicon oxide.
16. The method of claim 1 , wherein each of the second crack propagation guides includes an insulating material.
17. The method of claim 1 , further comprising:
forming an insulating layer that covers the second crack propagation guides and the second layer stack;
forming a test pattern on the insulating layer; and
forming a passivation layer that covers the test pattern.
18. A method of manufacturing a semiconductor chip, the method comprising:
forming a first layer stack by alternately stacking first material layers and second material layers over a semiconductor substrate, the semiconductor substrate including a chip region and a scribe lane region;
forming first trenches that overlap with the scribe lane region and second trenches that overlap with the chip region, the first and second trenches that substantially penetrate the first layer stack;
forming first crack propagation guides that fill the first trenches and insulating patterns that fill the second trenches;
forming a second layer stack by alternately stacking third material layers and fourth material layers on the first layer stack;
forming first openings that overlap with the scribe lane region and second openings that overlap with the chip region together, the first and second openings substantially penetrating the second layer stack; and
forming second crack propagation guides that fill the first openings and supporters filling the second openings.
19. The method of claim 18 , wherein each of the supporters and second crack propagation guides includes an insulating material.
20. The method of claim 18 , wherein the second openings and the supporters overlap with some portions of the insulating pattern.
21. The method of claim 18 , further comprising:
selectively removing portions of the second and fourth material layers that overlap with the chip region, the third and first material layers being supported by the supporters and the insulating pattern, the portions of the second and fourth material layers that overlap with the scribe lane region being maintained; and
filling portions from which the second and fourth material layers are removed with conductive layers for word lines.
22. The method of claim 21 , further comprising forming a slit that substantially penetrates the first and second layer stacks and overlaps with the chip region,
wherein the slit provides a passage through which the second and fourth material layers are removed.
23. The method of claim 18 , further comprising:
forming a channel hole that substantially penetrates the first and second layer stacks and overlaps with the chip region; and
forming a memory layer, a channel layer, and a filler on a sidewall of the channel hole.
24. The method of claim 23 ,
wherein the memory layer includes a tunnel layer, a charge trap layer, and a charge blocking layer,
wherein the channel layer includes a semiconductor material, and
wherein the filler includes an insulating material.
25. The method of claim 18 , wherein a plurality of second crack propagation guides overlap with the first crack propagation guides.
26. The method of claim 18 , wherein the plurality of first crack propagation guides are arranged side by side in the scribe lane region of the semiconductor substrate.
27. The method of claim 18 , wherein the first crack propagation guides include line patterns that are elongated across the scribe lane region of the semiconductor substrate.
28. The method of claim 18 , wherein the first openings are formed to expose portions of the first crack propagation guides.
29. The method of claim 18 , wherein each of the first openings has a through-hole shape.
30. The method of claim 18 , wherein the first material layer includes silicon oxide, and
wherein the second material layer includes silicon nitride.
31. The method of claim 18 , wherein the third material layer includes silicon oxide, and
wherein the fourth material layer includes silicon nitride.
32. The method of claim 18 , wherein the first and third material layers include the same insulating material,
wherein the second and fourth material layers include the same insulating material, and
wherein the first and second material layers include different insulating materials.
33. The method of claim 18 , wherein the first crack propagation guides include silicon oxide.
34. The method of claim 18 , further comprising:
forming an insulating layer that covers the second crack propagation guides and the second layer stack;
forming a conductive pattern and a test pattern on the insulating layer; and
forming a passivation layer that covers the conductive pattern and the test pattern.