Delay-compensating power management integrated circuit
A delay-compensating power management integrated circuit (PMIC) is provided. The PMIC includes a target voltage circuit configured to generate a target voltage that is utilized for generating a time-variant voltage to amplify an analog signal. The target voltage is generated based on a time-variant envelope of the analog signal but lags behind the time-variant envelope by a temporal delay(s) due to an inherent processing delay in the target voltage circuit. In this regard, a voltage processing circuit is provided in the target voltage circuit to generate a modified target voltage that is time-adjusted relative to the target voltage to substantially offset the temporal delay(s). By generating the time-variant voltage based on the modified target voltage, the time-variant voltage can be better aligned with the time-variant envelope of the analog signal, thus helping to reduce amplitude distortion when amplifying the analog signal.
1. A power management integrated circuit (PMIC) comprising:
a target voltage circuit comprising:
an envelope detector circuit configured to detect a time-variant envelope of an analog signal, wherein the detected time-variant envelope is delayed from the time-variant envelope of the analog signal by a first temporal delay;
an analog look-up table (LUT) circuit configured to generate a target voltage based on the detected time-variant envelope of the analog signal, wherein the target voltage is delayed from the detected time-variant envelope of the analog signal by a second temporal delay; and
a voltage processing circuit configured to generate a modified target voltage that is time-adjusted relative to the time-variant envelope of the analog signal to thereby substantially offset at least the first temporal delay and the second temporal delay.
2. The PMIC of claim 1 wherein the first temporal delay and the second temporal delay are predetermined and stored in the voltage processing circuit.
3. The PMIC of claim 1 wherein the target voltage circuit further comprises a delay detector circuit configured to:
dynamically determine the first temporal delay and the second temporal delay; and
provide the determined first temporal delay and the determined second temporal delay to the voltage processing circuit.
4. The PMIC of claim 1 wherein the analog LUT circuit comprises:
an average power tracking (APT) LUT that correlates the time-variant envelope of the analog signal with a constant target voltage corresponding to an average power of the analog signal; and
an envelope tracking (ET) LUT that correlates the time-variant envelope of the analog signal with a time-variant target voltage that tracks the time-variant envelope of the analog signal.
5. The PMIC of claim 4 wherein the analog LUT circuit is further configured to generate the target voltage based on one of the APT LUT and the ET LUT.
6. The PMIC of claim 1 wherein the voltage processing circuit is further configured to generate the modified target voltage as a function of a modulated modifier.
7. The PMIC of claim 6 wherein the voltage processing circuit is further configured to generate the modified target voltage based on an equation expressed as:
V TGT-R ( t )= V TGT ( t )+ K MOD ( t )*( V TGTMAX −V TGT ( t ));
wherein:
V TGT-R (t) represents the modified target voltage;
V TGT (t) represents the target voltage generated by the analog LUT circuit;
K MOD (t) represents the modulated modifier; and
V TGTMAX represents an estimated maximum value of the target voltage V TGT (t).
8. The PMIC of claim 6 wherein the voltage processing circuit is further configured to determine the modulated modifier as a function of a linear term and a nonlinear term.
9. The PMIC of claim 8 wherein the voltage processing circuit is further configured to determine the modulated modifier based on an equation expressed as:
K MOD ( t )= K MODLINEAR ( t )* NL GAIN ( dV TGT ( t )/ dt );
wherein:
K MOD (t) represents the modulated modifier;
K MODLINEAR (t) represents the linear term; and
NL GAIN (dV TGT (t)/dt) represents the nonlinear term.
10. The PMIC of claim 8 wherein the voltage processing circuit is further configured to determine the linear term as a function of a delay budget and a voltage offset corresponding to the delay budget.
11. The PMIC of claim 10 wherein the delay budget comprises at least the first temporal delay and the second temporal delay.
12. The PMIC of claim 11 wherein the voltage offset is predetermined based on the delay budget and stored in the voltage processing circuit.
13. The PMIC of claim 10 wherein the voltage processing circuit is further configured to determine the linear term based on an equation expressed as:
K MODLINEAR ( t )= K OFFSET ( dT )+[ dV TGT ( t )/ dt]*dT/[V TGTMAX −V TGT ( t )];
wherein:
K MODLINEAR (t) represents the linear term;
dT represents the delay budget;
K OFFSET (dT) represents the voltage offset corresponding to the delay budget;
V TGT (t) represents the target voltage generated by the analog LUT circuit; and
V TGTMAX represents an estimated maximum value of the target voltage V TGT (t).
14. The PMIC of claim 10 wherein:
the time-variant envelope of the analog signal comprises a plurality of amplitude peaks;
the modified target voltage comprises a plurality of voltage peaks each corresponding to a respective one of the plurality of amplitude peaks; and
the voltage offset is selected to cause each of the plurality of voltage peaks to be higher than the respective one of the plurality of amplitude peaks.
15. The PMIC of claim 1 further comprising an envelope tracking integrated circuit (ETIC) configured to generate a time-variant voltage for amplifying the analog signal, wherein the time-variant voltage is delayed from the target voltage by a third temporal delay.
16. The PMIC of claim 15 wherein the voltage processing circuit is further configured to generate the modified target voltage that is time-adjusted to offset the first temporal delay, the second temporal delay, and the third temporal delay.
17. The PMIC of claim 16 wherein the first temporal delay, the second temporal delay, and the third temporal delay are predetermined and stored in the voltage processing circuit.
18. The PMIC of claim 16 wherein the target voltage circuit further comprises a delay detector circuit configured to:
dynamically determine the first temporal delay, the second temporal delay, and the third temporal delay; and
provide the determined first temporal delay, the determined second temporal delay, and the determined third temporal delay to the voltage processing circuit.
19. The PMIC of claim 1 wherein the envelope detector circuit, the analog LUT circuit, and the voltage processing circuit are integrated into an integrated circuit.
20. A power management integrated circuit (PMIC) comprising:
a target voltage circuit comprising:
an envelope detector circuit configured to detect a time-variant envelope of an analog signal, wherein the detected time-variant envelope is delayed from the time-variant envelope of the analog signal by a first temporal delay;
an analog look-up table (LUT) circuit configured to generate a target voltage based on the detected time-variant envelope of the analog signal, wherein the target voltage is delayed from the detected time-variant envelope of the analog signal by a second temporal delay; and
a voltage processing circuit configured to generate a modified target voltage that is time-adjusted relative to the time-variant envelope of the analog signal to substantially offset at least the first temporal delay and the second temporal delay; and
an envelope tracking integrated circuit (ETIC) configured to generate a time-variant voltage based on the modified target voltage for amplifying the analog signal.