Arrays of capacitors and arrays of memory cells
A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes. Upper capacitor electrode material is formed over the capacitor insulator and the lower capacitor electrodes. A horizontally-elongated conductive line is formed atop individual of the groups that directly electrically couple together the upper capacitor electrode material there-below in that individual group.
1. An array of capacitors comprising:
a plurality of horizontally-spaced groups individually comprising a plurality of horizontally-spaced lower capacitor electrodes;
a capacitor insulator over the lower capacitor electrodes;
an upper capacitor electrode that is common to all capacitors in an individual group comprised by the plurality of horizontally-spaced groups; the capacitors in the individual group comprising one of the lower capacitor electrodes, the capacitor insulator, and the common upper capacitor electrode;
a horizontally-elongated conductive line atop and directly electrically coupled with the upper capacitor electrode in the individual group; and
horizontally-spaced pillars between immediately-adjacent individual groups comprised by the plurality of horizontally-spaced individual groups, the pillars being of a same size and shape relative to the lower capacitor electrodes and being circuit inoperative.
2. The array of claim 1 wherein the immediately-adjacent groups are horizontally spaced farther apart than are closest-immediately-adjacent of the lower capacitor electrodes within the groups.
3. The array of claim 1 wherein the pillars are on pitch with the lower capacitor electrodes in their immediately-adjacent groups.
4. The array of claim 3 wherein the lower capacitor electrodes are of the same size and shape relative one another, the pillars being of the same size and shape as the lower capacitor electrodes.
5. The array of claim 1 wherein the groups are horizontally-elongated in a column direction, the pillars between the immediately-adjacent individual groups being horizontally-spaced in at least one column along the column direction.
6. The array of claim 5 wherein all of the pillars that are between the immediately-adjacent individual groups are arrayed in one and only one column along the column direction.
7. The array of claim 6 wherein the pillars are on pitch with the lower capacitor electrodes in their immediately-adjacent groups.
8. The array of claim 1 wherein the pillars are 100% insulative.
9. The array of capacitors of claim 1 further comprising an array of transistors below the array of capacitors, the transistors individually being directly electrically coupled to individual of the lower capacitor electrodes.
10. The array of capacitors of claim 9 wherein the transistors are vertical transistors.
11. The array of capacitors of claim 10 comprising an array of memory cells individually comprising one of the capacitors and one of the transistors.
12. An array of ferroelectric memory cells individually comprising a ferroelectric capacitor above a transistor, comprising:
rows and columns of vertical transistors, a gateline line interconnecting multiple of the transistors along individual of the rows in a row direction, a plurality of digitlines with each digitline interconnecting multiple of the transistors along individual of the columns in a column direction, the transistors individually comprising a lower source/drain region directly electrically coupled with individual of the digitlines, the transistors individually comprising an upper source/drain region;
a plurality of horizontally-spaced groups individually comprising a plurality of horizontally-spaced lower capacitor electrodes, individual of the lower capacitor electrodes being directly above and directly electrically coupled to individual of the upper source/drain regions, immediately adjacent of the horizontally-spaced groups being horizontally spaced apart from one another by a gap that is horizontally elongated in the column direction;
a ferroelectric capacitor insulator over the lower capacitor electrodes;
an upper capacitor electrode that is common to all capacitors in individual groups comprised by the plurality of horizontally-spaced groups; the capacitors in the individual groups individually comprising one of the lower capacitor electrodes, the capacitor insulator, and the common upper capacitor electrode in the respective individual group;
a horizontally-elongated conductive line atop and directly electrically coupled with the upper capacitor electrode in the individual groups; and
horizontally-spaced pillars in the gap between immediately-adjacent of the individual groups, the pillars being of a same size and shape relative to the lower capacitor electrodes and being circuit inoperative.
13. The array of claim 12 wherein the immediately-adjacent groups are horizontally spaced farther apart than are closest-immediately-adjacent of the lower capacitor electrodes within the groups.
14. The array of claim 12 wherein the pillars are on pitch with the lower capacitor electrodes in their immediately-adjacent groups.
15. The array of claim 12 wherein the pillars are 100% insulative.
16. An array of ferroelectric memory cells individually comprising a ferroelectric capacitor above a transistor, comprising:
rows and columns of vertical transistors, a gateline line interconnecting multiple of the transistors along individual of the rows in a row direction, a plurality of digitlines with each digitline interconnecting multiple of the transistors along individual of the columns in a column direction, the transistors individually comprising a lower source/drain region directly electrically coupled with individual of the digitlines, the transistors individually comprising an upper source/drain region;
a plurality of horizontally-spaced groups individually comprising a plurality of horizontally-spaced lower capacitor electrodes, individual of the lower capacitor electrodes being directly above and directly electrically coupled to individual of the upper source/drain regions, immediately adjacent of the horizontally-spaced groups being horizontally spaced apart from one another by a gap that is horizontally elongated in the column direction;
a ferroelectric capacitor insulator over the lower capacitor electrodes;
an upper capacitor electrode that is common to all capacitors in individual groups comprised by the plurality of horizontally-spaced groups; the capacitors in the individual groups individually comprising one of the lower capacitor electrodes, the capacitor insulator, and the common upper capacitor electrode in the respective individual group;
a horizontally-elongated conductive line atop and directly electrically coupled with the upper capacitor electrode in the individual groups; and
horizontally-spaced pillars in the gap between immediately-adjacent of the individual groups, the pillars being circuit inoperative, all of the pillars that are between the immediately-adjacent individual groups being arrayed in one and only one column along the column direction.