System architecture, structure and method for hybrid random access memory in a system-on-chip
A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
1. A system architecture for hybrid random access memory in a system-on-chip, comprising:
a computing unit;
a hybrid register coupled to said computing unit;
multiple magnetoresistive random access memory (MRAM) blocks, wherein each of said MRAM blocks comprises multiple MRAM cells coupled to a MRAM controller, and said MRAM controller is coupled to said hybrid register; and
multiple resistive random-access memory (ReRAM) blocks, wherein each of said ReRAM blocks comprises multiple ReRAM cells coupled to a ReRAM controller, and said ReRAM controller is coupled to said hybrid register;
wherein said ReRAM cells and said MRAM cells are on the same semiconductor substrate.
2. The system architecture for hybrid random access memory in a system-on-chip according to claim 1 , wherein said MRAM blocks are coupled to said ReRAM blocks.
3. The system architecture for hybrid random access memory in a system-on-chip according to claim 1 , wherein each of said MRAM blocks further comprises:
a hot spare coupled to said MRAM cells;
a data backup unit coupled to said MRAM controller; and
a redundant array of independent drivers (RAID) fail unit coupled to said MRAM controller.
4. The system architecture for hybrid random access memory in a system-on-chip according to claim 1 , wherein each of said ReRAM blocks further comprises:
a hot spare coupled to said ReRAM cells; and
a RAID fail unit coupled to said ReRAM controller.
5. The system architecture for hybrid random access memory in a system-on-chip according to claim 1 , wherein said hybrid register comprises a high-speed data register and a low-speed data register.
6. The system architecture for hybrid random access memory in a system-on-chip according to claim 1 , wherein said computing unit comprises:
a chip;
a high-speed data computing controller coupled to said chip;
a low-speed data computing controller coupled to said chip;
a processor coupled to said chip; and
a cache coupled to said processor.