In-memory device for operating multi-bit weight

1. A multi-bit memory cell array, comprising:

one or more multi-bit units, each of which stores input data in each of a plurality of multi-bit application nodes based on an input signal, groups the plurality of multi-bit application nodes into a plurality of groups, and outputs a per-group sum value summed for each group by applying a multi-bit weight to the stored input data of each of the multi-bit application nodes; and

a final summation unit which is connected through a switch to the one or more multi-bit units, adjusts a ratio for each group to receive a per-group sum value based on a switching operation of the switch, and outputs a final output value by summing the input per-group sum value,

wherein each of the one or more multi-bit units includes:

a weight storing unit which is supplied with a power voltage between a first bit line and a second bit line and stores multi-bit weights based on the power voltage;

a multi-bit weight application unit which includes the plurality of multi-bit application nodes connected in parallel and applies one bit weight among the multi-bit weights to the input data stored in a capacitor connected to each of the plurality of multi-bit application nodes to output a weight applied value; and

a per-group summation unit which groups the plurality of multi-bit application nodes into the plurality of groups to sum the weight applied value for each group to output a sum value for each group.

2. The multi-bit cell array according to claim 1 , wherein the multi-bit weight application unit stores the input data in the capacitor through an input voltage corresponding to the input signal applied to the plurality of multi-bit application nodes and when the bit weight is input by a predetermined switching operation, applies the bit weighted value to the input data in each multi-bit application node to output the weight applied value.

3. The multi-bit cell array according to claim 2 , wherein the capacitors connected to the plurality of multi-bit application nodes have different capacitances or only some of the capacitors have the same capacitance and the multi-bit weight application unit applies the bit weight to the input data corresponding to the capacitance in each of the plurality of multi-bit application nodes to output the weight applied value.

4. The multi-bit cell array according to claim 3 , wherein the multi-bit weight application unit outputs the weight applied value calculated by multiplying the bit weighted value and the input data in each of the plurality of multi-bit application nodes.

5. The multi-bit cell array according to claim 3 , wherein the per-group summation unit includes:

a first weight sum processing unit which outputs a first group sum value calculated by summing a plurality of weight applied values output from the multi-bit application nodes included in a first group among the plurality of multi-bit application nodes; and

a second weight sum processing unit which outputs a first group sum value calculated by summing a plurality of weight applied values output from the multi-bit application nodes included in a second group among the plurality of multi-bit application nodes; and

the multi-bit application nodes included in the first group are different from the multi-bit application nodes included in the second group.

6. The multi-bit cell array according to claim 5 , wherein the per-group summation unit allows a multi-bit application node corresponding to upper bit weight of upper digits among the multi-bit weight to be included in the first group to output the first group sum value and allows a multi-bit application node corresponding to a lower bit weight of lower digits excluding the upper bit weight from the multi-bit weights to be included in the second group to output the second group sum value.

7. The multi-bit cell array according to claim 6 , wherein the final summation unit includes:

a first final summation line which receives the first group sum value output from the at least one multi-bit unit to calculate a first final sum value; and

a second final summation line which receives the second group sum value output from the at least one multi-bit unit to calculate a second final sum value,

the final summation unit adjusts the first group sum value and the second group sum value at a specific ratio according to a switching operation of a first final switch connected between at least one multi-bit unit and the first final summation line and a second final switch connected between at least one multi-bit unit and the second final summation line, and sums the first final sum value and the second final sum value by a switching operation of a third final switch connected between the first final summation line and the second final summation line to output the final output value.

8. An in-memory device, comprising:

a plurality of bit lines and a plurality of word lines;

a DAC which converts a digital input signal into an analog input voltage;

a memory cell array which includes at least one multi-bit memory cell which stores a multi-bit weight and input data based on an input voltage and performs multiplication and summation for each group using the multi-bit weight and the input data to output a final output value; and

an ADC which receives the final output value and converts the final output value into a digital output signal,

wherein the memory cell array includes:

one or more multi-bit units, each of which stores input data in each of a plurality of multi-bit application nodes based on the input signal, groups the plurality of multi-bit application nodes into a plurality of groups, and outputs a per-group sum value summed for each group by applying a multi-bit weight to the stored input data of each of the plurality of multi-bit application nodes; and

a final summation unit which is connected through a switch to the one or more multi-bit units, adjusts a ratio for each group to receive the per-group sum value based on a switching operation of the switch, and outputs a final output value by summing the input per-group sum value,

wherein each of the one or more multi-bit units includes:

a weight storing unit which is supplied with a power voltage between a first bit line and a second bit line and stores multi-bit weights based on the power voltage;

a multi-bit weight application unit which includes the plurality of multi-bit application nodes connected in parallel and applies one bit weight among the multi-bit weights to the input data stored in a capacitor connected to each of the plurality of multi-bit application nodes to output a weight applied value; and

a per-group summation unit which divides the plurality of multi-bit application nodes into the plurality of groups to sum the weight applied value for each group to output a per-group sum value.

9. The in-memory device according to claim 8 , wherein

the multi-bit weight application unit stores the input data in the capacitor through an input voltage corresponding to the input signal applied to the plurality of multi-bit application nodes and when the bit weight is input by a predetermined switching operation, applies the bit weighted value to the input data in each multi-bit application node to output the weight applied value, and

the capacitors connected to the plurality of multi-bit application nodes have different capacitances or only some of the capacitors have the same capacitance and the multi-bit weight application unit applies the bit weight to the input data corresponding to the capacitance in each of the plurality of multi-bit application nodes to output the weight applied value.