Electronic memory devices
A memory cell comprises a floating gate being disposed between a control gate and a channel, the floating gate being electrically isolated from the control gate and the channel by charge barriers and being configured to enable the selective passage of charge carriers into and out of the floating gate to provide occupancy states of the floating gate. The channel is arranged to provide a minimum threshold voltage to be applied between a control gate and the substrate for introducing charge carriers into the channel from the substrate to make the channel conductive, the minimum threshold voltage being dependent on the occupancy state of the floating gate, such that a read voltage may be applied between the control gate and the substrate that will provide a conductive channel for a first occupancy state of the floating gate and a non-conductive channel for a second occupancy state of the floating gate.
1. A memory cell for storing one or more bits of information, the memory cell comprising:
a semiconductor substrate on which is provided a source terminal, a drain terminal, and a channel extending between the source terminal and the drain terminal; and
a control gate and a floating gate, the floating gate being disposed between the control gate and the channel, and the floating gate being electrically isolated from the control gate and the channel by charge barriers and being configured to enable selective passage of charge carriers into and out of the floating gate, in write and erase operations, to provide at least first and second occupancy states of the floating gate, the channel being arranged to provide a minimum threshold voltage to be applied between the control gate and the semiconductor substrate for introducing charge carriers into the channel from the semiconductor substrate to make the channel conductive, the minimum threshold voltage being dependent on an occupancy state of the floating gate, such that a read voltage may be applied between the control gate and the semiconductor substrate that will provide a conductive channel for the first occupancy state of the floating gate and a non-conductive channel for the second occupancy state of the floating gate,
wherein an interface between the channel and the semiconductor substrate is a type-III heterojunction,
wherein the channel comprises a quantum well, a quantum dot, or a quantum wire having discrete confined energy levels for accommodating charge carriers in the channel, and
wherein a lowest confined energy level of the quantum well, the quantum dot, or the quantum wire in an absence of an electric field applied across the memory cell is at a higher energy than a valence band of the semiconductor substrate.
2. The memory cell according to claim 1 , wherein the quantum well, the quantum dot, or the quantum wire is defined between a charge barrier and the semiconductor substrate.
3. The memory cell according to claim 2 , wherein the charge barrier and the semiconductor substrate define walls of the quantum well, the quantum dot, or the quantum wire.
4. The memory cell according to claim 1 , wherein in an absence of any applied bias across the channel the channel comprises an electric potential barrier at an interface between the channel and a charge barrier, and an electric potential barrier at the interface between the channel and the semiconductor substrate, and
wherein the electric potential barrier at the interface between the channel and the semiconductor substrate enables selective passage of charge carriers between the semiconductor substrate and the channel.
5. The memory cell according to claim 4 , wherein at least one of:
the selective passage of charge carriers between the semiconductor substrate and the channel, in use, is controllable by controlling at least one of a shape or a magnitude of the electric potential barrier at the interface between the channel and the semiconductor substrate, or
the selective passage of charge carriers between the semiconductor substrate and the channel is controllable by application of an electric field across the memory cell.
6. The memory cell according to claim 1 , wherein in response to application of an electric field, the lowest confined energy level of the quantum well, the quantum dot, or the quantum wire has a lower energy than a valence band energy of at least a portion of the semiconductor substrate.
7. The memory cell according to claim 1 , wherein the channel is formed by having at least one of offset conduction or valence bands to form heterojunctions at an interface between the channel and a charge barrier, and at the interface between the channel and the semiconductor substrate.
8. The memory cell according to claim 1 , wherein the channel is formed by a narrow band gap semiconductor being disposed between two wide band gap semiconductors.
9. The memory cell according to claim 1 , wherein the channel is formed by indium gallium arsenide (InGaAs), and an adjacent barrier material is gallium antimonide (GaSb).
10. The memory cell according to claim 1 , wherein the lowest confined energy level of the quantum well, the quantum dot, or the quantum wire has a higher energy than a Fermi energy of the semiconductor substrate in the absence of an electric field applied across the memory cell.
11. The memory cell according to claim 1 , wherein the channel is unoccupied by charge carriers in the absence of an applied electric field.
12. The memory cell according to claim 1 , wherein the channel is at least one of non-conductive or insulating in the absence of an applied electric field.
13. A memory device comprising a plurality of memory cells as claimed in claim 1 , wherein the floating gate is configured to enable the selective passage of charge carriers into and out of the floating gate by resonant tunnelling, in write and erase operations.
14. The memory device as claimed in claim 13 , wherein the plurality of memory cells are arranged in an array comprising a plurality of columns and a plurality of rows, and the memory device comprises at least one first electrical contact arranged to provide a voltage to the control gate of each memory cell in a column of the array, and at least one second electrical contact arranged to provide a voltage to at least one of the source terminal, the drain terminal, or a base gate terminal.
15. The memory device as claimed in claim 14 , wherein the first electrical contact is configured to apply a first portion of a required voltage to a desired column within the array, and the second electrical contact is configured to apply a second portion of the required voltage to a desired row within the array, such that a target cell within the array receives a full required voltage.
16. The memory device as claimed in claim 15 , wherein the required voltage is any of the read voltage, write voltage and erase voltage.
17. The memory device as claimed in claim 13 , wherein either source terminals of a plurality of memory cells or drain terminals of the plurality of memory cells are electrically connected to a base gate terminal that is common to the plurality of memory cells.