IP Library › Granted Patent US 11,929,279
Granted Patent B2
US 11,929,279 · App. 17/152,390 · Granted Mar 12, 2024

Semiconductor device including semiconductor liner and method for fabricating the same

Inventor: Jin Woong Kim (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
H01L21/76224H01L21/0245H01L21/02502H01L21/02661H01L21/02664H10B12/34H01L21/76229
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,929,279
App. No.
17/152,390
Granted
Mar 12, 2024
Kind
B2
Abstract

A semiconductor device including: a trench defining an active region in a substrate; a first semiconductor liner formed over the trench; a second semiconductor liner formed over the first semiconductor liner; and a device isolation layer formed over the second semiconductor liner and filling the trench. Disclosed is also a method for fabricating a semiconductor device, the method including: forming a trench defining an active region in a substrate; forming a plurality of semiconductor liners over the trench; performing pretreatment before forming each of the semiconductor liners; and performing post-treatment after forming each of the semiconductor liners.

Claims (37)

1. A method for fabricating a semiconductor device, the method comprising:

forming a trench defining an active region in a substrate;

forming a plurality of semiconductor liners over the trench;

performing a pretreatment before forming each of the semiconductor liners;

performing a post-treatment after forming each of the semiconductor liners; and

forming a device isolation layer filling the trench over the plurality of semiconductor liners after performing the post-treatment,

wherein the plurality of semiconductor liners are formed by stacking polysilicon (poly-Si).

2. The method of claim 1 , wherein the performing of the pretreatment comprises:

replacing a contaminant generated before forming each of the semiconductor liners with a sacrificial material; and

performing heat treatment to remove the sacrificial material.

3. The method of claim 2 , wherein the replacing of the contaminant with the sacrificial material is performed using a reactive gas having reactivity with the contaminant.

4. The method of claim 3 , wherein the reactive gas is formed using ammonia (NH 3 ) gas, nitrogen trifluoride (NF 3 ) gas and hydrogen (H 2 ) gas.

5. The method of claim 2 , wherein

the contaminant comprises silicon oxide, and

the sacrificial material comprises ammonium hexafluorosilicate ((NH 4 ) 2 SiF 6 ).

6. The method of claim 1 , wherein the post-treatment is performed at a higher temperature than the pretreatment.

7. The method of claim 1 , wherein the post-treatment is performed through an annealing process or a rapid thermal process (RTP).

8. The method of claim 1 , wherein the post-treatment is performed under a gas atmosphere containing one of nitrogen (N 2 ) and hydrogen (H 2 ).

9. The method of claim 1 , further comprising cleaning each of the semiconductor liners, before the performing of the post-treatment.

10. The method of claim 1 , wherein the pretreatment and the forming of the semiconductor liners are performed in situ.

11. The method of claim 1 , wherein the post-treatment is performed in one of a single equipment and a furnace equipment.

12. A method for fabricating a semiconductor device, the method comprising:

forming a trench defining an active region in a substrate;

performing a first pretreatment in which a native oxide formed on the trench is replaced with a solid salt and the solid salt is sublimated to expose a surface of the trench;

forming a first polysilicon liner over the trench;

performing a post-treatment to remove a contaminant formed on the first polysilicon liner;

performing a second pretreatment in which a native oxide formed on the first polysilicon liner is replaced with a solid salt and the solid salt is sublimated to expose a surface of the first poly silicon liner;

forming a second polysilicon liner over the first polysilicon liner; and

forming a device isolation layer filing the trench over the second polysilicon liner.

13. The method of claim 12 , wherein the replacing of the native oxide with the solid salt is performed using a reactive gas having reactivity with the native oxide.

14. The method of claim 13 , wherein the reactive gas is formed using ammonia (NH 3 ) gas, nitrogen trifluoride (NF 3 ) gas and hydrogen (H 2 ) gas.

15. The method of claim 12 , wherein the solid salt comprises ammonium hexafluorosilicate ((NH 4 ) 2 SiF 6 ).

16. The method of claim 12 , wherein the post-treatment is performed at a higher temperature than the sublimating of the solid salt.

17. The method of claim 12 , wherein the post-treatment is performed through an annealing process or a rapid thermal process (RTP).

18. The method of claim 12 , wherein the post-treatment is performed under a gas atmosphere containing one of nitrogen (N 2 ) and hydrogen (H 2 ).

19. The method of claim 12 , further comprising cleaning the first polysilicon liner, before the performing of the post-treatment.

20. The method of claim 12 , wherein the post-treatment is performed in one of a single equipment and a furnace equipment.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2021
From: KIM, JIN WOONG
To: SK HYNIX INC.
Reel/Frame 054956/0441 →
Priority Claims (1)
KR 10-2020-0124457 · Sep 25, 2020 · national
Continuity (1)
Related Publication 20220102193A1 · Mar 31, 2022