Thin film transistors with offset source and drain structures and process for forming such
A device is disclosed. The device includes a source contact and a drain contact, a first dielectric between the source contact and the drain contact, a channel under the source contact and the drain contact, and a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact. A second dielectric is above the gate electrode and underneath the channel.
1. A device, comprising:
a source contact and a drain contact;
a first dielectric between the source contact and the drain contact, the first dielectric having an uppermost surface at a same level as an uppermost surface of the source contact and the drain contact;
a channel under the source contact and the drain contact;
a gate electrode below the channel, the gate electrode in an area under the first dielectric that does not laterally extend under the source contact or the drain contact;
a second dielectric above the gate electrode and underneath the channel; and
an interconnect layer beneath the gate electrode, the interconnect layer extending laterally beyond the source contact and the drain contact along a direction from the source contact to the drain contact.
2. The device of claim 1 , wherein the gate electrode includes a conductive via.
3. The device of claim 1 , further comprising an etch stop layer, wherein the gate electrode is formed in the etch stop layer.
4. The device of claim 1 , wherein the bottom of the gate electrode is directly connected to the interconnect layer.
5. The device of claim 1 , wherein the width of the gate electrode is from 20 to 40 nm.
6. The device of claim 1 , wherein the thickness of the gate electrode is from 10 to 30 nm.
7. The device of claim 1 , wherein the source contact and the drain contact include a plurality of layers of materials.
8. A system, comprising:
one or more processing components; and
one or more data storage components, the data storage components including at least one device, the at least one device including:
a source contact and a drain contact;
a first dielectric between the source contact and the drain contact, the first dielectric having an uppermost surface at a same level as an uppermost surface of the source contact and the drain contact;
a channel under the source contact and the drain contact;
a gate electrode below the channel, the gate electrode occupying an area under the first dielectric that does not laterally extend under the source contact or the drain contact;
a second dielectric above the gate electrode and underneath the channel; and
an interconnect layer beneath the gate electrode, the interconnect layer extending laterally beyond the source contact and the drain contact along a direction from the source contact to the drain contact.
9. The system of claim 8 , wherein the gate electrode includes a conductive via.
10. The system of claim 8 , further comprising an etch stop layer, wherein the gate electrode is formed in the etch stop layer.
11. The system of claim 8 , wherein the bottom of the gate electrode is directly connected to the interconnect layer.
12. The system of claim 8 , wherein the width of the gate electrode is from 20 to 40 nm.
13. The system of claim 8 , wherein the thickness of the gate electrode is from 10 to 30 nm.
14. The system of claim 8 , wherein the source contact and the drain contact include a plurality of layers of materials.