IP Library › Granted Patent US 11,930,184
Granted Patent B2
US 11,930,184 · App. 17/428,359 · Granted Mar 12, 2024

Motion vector derivation in video encoding and decoding

Inventors: Fabrice Urban (Thorigne Fouillard, FR); Franck Galpin (Thorigne-Fouillard, FR); Philippe Bordes (Laille, FR)
Assignee: InterDigital CE Patent Holdings, SAS
H04N19/137H04N19/172H04N19/513H04N19/70
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Quick Facts
Patent No.
US 11,930,184
App. No.
17/428,359
Granted
Mar 12, 2024
Kind
B2
Abstract

Video processing can involve encoding and/or decoding a picture based on determining an activation of a processing mode involving a motion vector refinement process and a second process other than the motion vector refinement process; modifying the motion vector refinement process based on the activation and the second process; and encoding and/or decoding the picture based on the modified motion vector refinement process and the second process.

Claims (32)

1. A method for encoding a picture, comprising:

determining an activation of a processing mode involving a decoder side motion vector refinement (DMVR) process and a local illumination compensation (LIC) process;

modifying the DMVR process based on the activation; and

encoding the picture based on the modified DMVR process, wherein modifying the DMVR process comprises modifying a cost function associated with the DMVR process, and modifying the cost function comprises using a mean removed sum of absolute differences (MRSAD) cost function during the DMVR process.

2. A non-transitory computer readable medium storing executable program instructions to cause a computer executing the instructions to perform a method according to claim 1 .

3. The method of claim 1 , wherein using the MRSAD cost function during the DMVR process comprises calculating a constant offset between two video blocks and removing the constant offset from a sum of absolute differences between the two video blocks.

4. The method of claim 3 , wherein the DMVR process involves at least a first search point and a second search point, and wherein the constant offset is calculated for the first search point and reused for the second search point.

5. A method for decoding a picture, comprising:

determining an activation of a processing mode involving a decoder side motion vector refinement (DMVR) process and a local illumination compensation (LIC) process;

modifying the DMVR process based on the activation; and

decoding the picture based on the modified DMVR process, wherein modifying the DMVR process comprises modifying a cost function associated with the DMVR process, and modifying the cost function comprises using a mean removed sum of absolute differences (MRSAD) cost function during the DMVR process.

6. A non-transitory computer readable medium storing executable program instructions to cause a computer executing the instructions to perform a method according to claim 5 .

7. The method of claim 5 , wherein using the MRSAD cost function during the DMVR process comprises calculating a constant offset between two video blocks and removing the constant offset from a sum of absolute differences between the two video blocks.

8. The method of claim 7 , wherein the DMVR process involves at least a first search point and a second search point, and wherein the constant offset is calculated for the first search point and reused for the second search point.

9. The method of claim 5 , wherein decoding the picture based on the modified DMVR process comprises performing the modified DMVR process in parallel with the LIC process.

10. An apparatus for encoding a picture, comprising one or more processors, wherein the one or more processors are configured to:

determine an activation of a processing mode involving a decoder side motion vector refinement (DMVR) process and a local illumination compensation (LIC) process;

modify the DMVR process based on the activation and the LIC process; and

encode the picture based on the modified DMVR process and the LIC process, wherein the one or more processors being configured to modify the DMVR process comprises the one or more processors being configured to modify a cost function associated with the motion vector refinement process, and the one or more processors being configured to modify the cost function associated with the DMVR process comprises the one or more processors being configured to use a mean removed sum of absolute differences (MRSAD) cost function during the DMVR process.

11. The apparatus of claim 10 further comprising at least one of (i) an antenna configured to receive a signal, the signal including data representative of image information, (ii) a band limiter configured to limit the received signal to a band of frequencies that includes the data representative of the image information, and (iii) a display configured to display an image from the image information.

12. The apparatus of claim 11 , wherein the apparatus comprises one of a television, a television signal receiver, a set-top box, a gateway device, a mobile device, a cell phone, a tablet, or other electronic device.

13. The apparatus of claim 10 , wherein the processor being configured to use the MRSAD cost function during the DMVR process comprises the processor being configured to calculate a constant offset between two video blocks and remove the constant offset from a sum of absolute differences between the two video blocks.

14. The apparatus of claim 13 , wherein the DMVR process involves at least a first search point and a second search point, and wherein the constant offset is calculated for the first search point and reused for the second search point.

15. An apparatus for decoding a picture, comprising one or more processors, wherein the one or more processors are configured to:

determine an activation of a processing mode involving a decoder side motion vector refinement (DMVR) process and a local illumination compensation (LIC) process;

modify the DMVR process based on the activation and the LIC process; and

decode the picture based on the modified DMVR process and the LIC process, wherein the one or more processors being configured to modify the DMVR process comprises the one or more processors being configured to modify a cost function associated with the motion vector refinement process, and the one or more processors being configured to modify the cost function associated with the DMVR process comprises the one or more processors being configured to use a mean removed sum of absolute differences (MRSAD) cost function during the DMVR process.

16. The apparatus of claim 15 further comprising at least one of (i) an antenna configured to receive a signal, the signal including data representative of image information, (ii) a band limiter configured to limit the received signal to a band of frequencies that includes the data representative of the image information, and (iii) a display configured to display an image from the image information.

17. The apparatus of claim 16 , wherein the apparatus comprises one of a television, a television signal receiver, a set-top box, a gateway device, a mobile device, a cell phone, a tablet, or other electronic device.

18. The apparatus of claim 15 , wherein the processor being configured to use the MRSAD cost function during the DMVR process comprises the processor being configured to calculate a constant offset between two video blocks and remove the constant offset from a sum of absolute differences between the two video blocks.

19. The apparatus of claim 18 , wherein the DMVR process involves at least a first search point and a second search point, and wherein the constant offset is calculated for the first search point and reused for the second search point.

20. The apparatus of claim 15 , wherein the processor being configured to decode the picture based on the modified DMVR process comprises the processor being configured to perform the modified DMVR process in parallel with the LIC process.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2023
From: INTERDIGITAL VC HOLDINGS FRANCE, SAS
To: INTERDIGITAL CE PATENT HOLDINGS, SAS
Reel/Frame 064746/0496 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2021
From: URBAN, FABRICE; GALPIN, FRANCK; BORDES, PHILIPPE
To: INTERDIGITAL VC HOLDINGS FRANCE
Reel/Frame 057094/0690 →
Priority Claims (1)
EP 19305272 · Mar 8, 2019 · regional
Continuity (1)
Related Publication 20220116621A1 · Apr 14, 2022