IP Library › Granted Patent US 11,934,261
Granted Patent B2
US 11,934,261 · App. 17/580,408 · Granted Mar 19, 2024

Flit-based parallel-forward error correction and parity

Inventor: Debendra Das Sharma (Saratoga, CA)
Assignee: Intel Corporation
G06F11/1004G06F11/076G06F11/1402G06F13/4221H04L1/0041H04L1/0061H04L1/0083H04L1/009H04L1/1812
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Quick Facts
Patent No.
US 11,934,261
App. No.
17/580,408
Granted
Mar 19, 2024
Kind
B2
Abstract

A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme and a flit-level forward error correction or parallel-forward error correction (FEC) scheme. Flit-level FEC schemes can provide improved latencies and efficiencies over per-lane FEC schemes. To improve retry probability, flits can contain information indicating whether immediately preceding flits are null flits. Receivers can avoid sending a retry request for a corrupted flit if a seceding flit indicates the corrupted flit is a null fit. Parity flits can be used to protect groups of flits and correct single-flit errors.

Claims (70)

1. An apparatus comprising:

a port to send information on multiple lanes of a link;

protocol stack circuitry to:

create a transaction layer packet (TLP) to be transmitted on the link;

calculate error correcting code (ECC) for all of the transaction layer packets;

generate a flit comprising the transaction layer packet;

interleave the ECC in multiple symbols of the flit; and

cause the port to send the flit on the multiple lanes.

2. The apparatus of claim 1 , the protocol stack to interleave the ECC using 3-way interleaving.

3. The apparatus of claim 1 , wherein the ECC comprises parity and check bits.

4. The apparatus of claim 1 , the protocol stack to:

create data link layer packets (DLLP); and

encode the flit with data link layer packet into symbols after the transaction layer packets and before the ECC.

5. The apparatus of claim 4 , wherein the protocol stack is further to:

calculate cyclic redundancy check (CRC) code for the transaction layer packets, the CRC code comprising eight bytes;

encode eight consecutive symbols of the flit with the CRC code after the transaction layer packets.

6. The apparatus of claim 5 , wherein the CRC code is to check the TLPs and the DLLPs in the flit.

7. The apparatus of claim 5 , wherein the ECC is interleaved into the flit after the CRC code.

8. The apparatus of claim 5 , wherein the ECC is to check the TLPs, the DLLPs, and the CRC code.

9. The apparatus of claim 1 , wherein the ECC comprises six bytes interleaved across six symbols of the flit.

10. A method, comprising:

creating transaction layer packet (TLP) to be transmitted on multiple lanes of a link;

calculating error correcting code (ECC) for the transaction layer packet;

generating a flit comprising the transaction layer packets;

interleaving the ECC in multiple symbols of the flit, wherein the ECC is for the entire Flit payload; and

transmitting the flit on the link.

11. The method of claim 10 , further comprising interleaving the ECC using 3-way interleaving.

12. The method of claim 10 , wherein the ECC comprises parity and check bits.

13. The method of claim 10 , further comprising:

generating data link layer packets (DLLP); and

encoding the flit with data link layer packet into symbols after the transaction layer packets and before the ECC.

14. The method of claim 13 , further comprising:

calculating cyclic redundancy check (CRC) code for the transaction layer packets, the CRC code comprising eight bytes; and

encoding eight consecutive symbols of the flit with the CRC code after the transaction layer packets.

15. The method of claim 14 , wherein the CRC code is to check the TLPs and the DLLPs in the flit.

16. The method of claim 14 , wherein the ECC is interleaved into the flit after the CRC code.

17. The method of claim 14 , wherein the ECC is to check the TLPs, the DLLPs, and the CRC code.

18. The method of claim 10 , wherein the ECC comprises six bytes interleaved across six symbols of the flit.

19. A system comprising:

a link connecting a transmitter to a receiver;

the transmitter comprising a transmitter-side protocol stack circuitry to:

create transaction layer packets (TLP) to be transmitted on the link,

calculate error correcting code (ECC) for the transaction layer packets,

generate a flit comprising the transaction layer packets,

interleave the ECC in multiple symbols of the flit, and

transmit the flit on the link; and

the receiver comprising receiver-side protocol stack circuitry to:

receive the flit from across the link, and

check the TLP for errors using ECC received in the flit.

20. The system of claim 19 , the transmitter-side protocol stack circuitry to interleave the ECC using 3-way interleaving.

21. The system of claim 19 , the transmitter-side protocol stack circuitry to:

generate data link layer packets (DLLP); and

encode the flit with data link layer packet into symbols after the transaction layer packets and before the ECC.

22. The system of claim 21 , wherein the transmitter-side protocol stack circuitry is to:

calculate cyclic redundancy check (CRC) code for the transaction layer packets, the CRC code comprising eight bytes;

encode eight consecutive symbols of the flit with the CRC code after the transaction layer packets.

23. The system of claim 22 , wherein the CRC code is to check the TLPs and the DLLPs in the flit.

24. The system of claim 22 , wherein:

the ECC is interleaved into the flit after the CRC code; and

the ECC is to check the TLPs, the DLLPs, and the CRC code.

25. The system of claim 19 , wherein the ECC comprises six bytes interleaved across six symbols of the flit.

26. An apparatus comprising:

protocol stack circuitry to:

generate a flow control unit (Flit), the Flit comprising a predetermined number of bytes;

the Flit comprising:

a transaction layer packet (TLP) payload to occupy a first number of bytes of the Flit; and

error correcting code (ECC) to occupy six bytes of the Flit, the ECC to protect each byte of the TLP payload.

27. The apparatus of claim 26 , the protocol stack circuitry to:

calculate cyclic redundancy check (CRC) code for the transaction layer packet, the CRC code comprising eight bytes;

encode eight consecutive symbols of the flit with the CRC code after the transaction layer packets, the CRC to check the entire TLP payload.

Continuity (4)
Continuation 16575739 · Sep 19, 2019
Provisional Application 62837318 · Apr 23, 2019
Provisional Application 62812507 · Mar 1, 2019
Related Publication 20220147417A1 · May 12, 2022