Instruction scheduling in a processor using operation source parent tracking

1. A processor for scheduling instructions, comprising:

a scheduling entry array circuit comprising a plurality of scheduling entries, each scheduling entry configured to store first operation source parent information; and

a compare array circuit configured to:

receive the first operation source parent information from the scheduling entry array circuit; and

perform a dependency comparison with a first source parent of a plurality of source parents based on the first operation source parent information;

wherein:

each of the plurality of source parents is associated with an execution pipeline of a plurality of execution pipelines; and

the processor is configured to perform the dependency comparison by being configured to:

select, using the first operation source parent information, an associated execution pipeline from among the plurality of execution pipelines on which to perform the dependency comparison;

select, using the first operation source parent information, information from the associated execution pipeline; and

perform the dependency comparison only against the information from the associated execution pipeline.

2. The processor of claim 1 , further comprising a ready information array circuit comprising a plurality of ready entries, each ready entry associated with a scheduling entry, and each ready entry configured to store dependency information associated with the scheduling entry, and to update the dependency information based on the dependency comparison.

3. The processor of claim 2 , wherein each ready entry is configured to indicate:

the associated scheduling entry is not ready for scheduling when the stored dependency information includes at least one unresolved dependency; and

the associated scheduling entry is ready for scheduling when the stored dependency information includes no unresolved dependencies.

4. The processor of claim 3 , further comprising a picker circuit configured to indicate a scheduling entry of the plurality of scheduling entries for scheduling by a selection circuit based on at least one ready entry indicating no unresolved dependencies.

5. The processor of claim 4 , further comprising the selection circuit responsive to the picker circuit and configured to provide a scheduling entry to one of the plurality of execution pipelines based on the indication from the picking circuit.

6. The processor of claim 1 , further comprising a rename circuit configured to provide the first operation source parent information associated with a first instruction.

7. The processor of claim 1 , wherein each scheduling entry is configured to store a plurality of operation source parent information including the first operation source parent information.

8. The processor of claim 1 , wherein the compare array circuit is configured to provide an indication that no dependency exists when the first operation source parent information indicates that a first operation source parent is unused.

9. The processor of claim 1 , integrated into an integrated circuit (IC).

10. The processor of claim 1 , further integrated into a device selected from the group consisting of: a server, a computer, a portable computer, a desktop computer, a mobile computing device, a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

11. A processor, comprising:

a means for storing scheduling entries comprising a plurality of scheduling entries, each scheduling entry among the plurality of scheduling entries configured to store first operation source parent information;

a means for receiving the first operation source parent information from the means for storing the scheduling entries; and

a means for performing a dependency comparison with a first source parent of a plurality of source parents based on the first operation source parent information;

wherein:

each of the plurality of source parents is associated with an execution pipeline of a plurality of execution pipelines; and

the means for performing the dependency comparison comprises:

a means for selecting, using the first operation source parent information, an associated execution pipeline from among the plurality of execution pipelines on which to perform the dependency comparison;

a means for selecting, using the first operation source parent information, information from the associated execution pipeline; and

a means for performing the dependency comparison only against the information from the associated execution pipeline.

12. The processor of claim 11 , further comprising a means for storing ready information comprising a plurality of ready entries, each ready entry associated with a scheduling entry, and each ready entry configured to store dependency information associated with the scheduling entry, and to update the dependency information based on the dependency comparison.

13. A method of tracking operation source parent information in a processor, comprising:

establishing a first scheduler entry of a plurality of scheduler entries, the first scheduler entry comprising first operation source parent information;

providing the first operation source parent information to a parent selection circuit;

selecting a compare source parent from a plurality of source parents based on the first operation source parent information, wherein each of the plurality of source parents is associated with an execution pipeline of a plurality of execution pipelines; and

performing a dependency comparison associated with the first scheduler entry using the compare source parent;

wherein performing the dependency comparison comprises:

selecting, using the first operation source parent information, an associated execution pipeline from among the plurality of execution pipelines on which to perform the dependency comparison;

selecting, using the first operation source parent information, information from the associated execution pipeline; and

performing the dependency comparison only against the information from the associated execution pipeline.

14. The method of claim 13 , further comprising updating first dependency information in a first ready information array entry of a plurality of ready information array entries, the first ready information array entry associated with the first scheduler entry, based on the dependency comparison.

15. The method of claim 14 , further comprising selecting the first scheduler entry for scheduling on an execution pipeline of the plurality of execution pipelines based on the first dependency information in the first ready information array entry indicating that no unresolved dependencies exist.

16. The method of claim 13 , further comprising receiving the first operation source parent information from a rename circuit.

17. The method of claim 13 , wherein the dependency comparison is performed in response to establishing the first scheduler entry.

18. The method of claim 13 , wherein the dependency comparison is performed in response to an operation corresponding to a source parent of the plurality of source parents being completed.

19. A non-transitory computer-readable medium having stored thereon computer executable instructions which, when executed by a processor, cause the processor to:

establish a first scheduler entry of a plurality of scheduler entries, the first scheduler entry comprising first operation source parent information;

provide the first operation source parent information to a parent selection circuit;

select a compare source parent from a plurality of source parents based on the first operation source parent information, wherein each of the plurality of source parents is associated with an execution pipeline of a plurality of execution pipelines; and

perform a dependency comparison associated with the first scheduler entry using the compare source parent;

wherein the computer executable instructions cause the processor to perform the dependency comparison by causing the processor to:

select, using the first operation source parent information, an associated execution pipeline from among the plurality of execution pipelines on which to perform the dependency comparison;

select, using the first operation source parent information, information from the associated execution pipeline; and

perform the dependency comparison only against the information from the associated execution pipeline.

20. The non-transitory computer-readable medium of claim 19 , further having stored thereon computer executable instructions which, when executed by a processor, cause the processor to update first dependency information in a first ready information array entry of a plurality of ready information array entries, the first ready information array entry associated with the first scheduler entry, based on the dependency comparison.