Methods of inspection of semiconductor packages including measurement of alignment accuracy among semiconductor chips
A semiconductor package may include first and second substrates, which are vertically stacked, a semiconductor device layer on a bottom surface of the second substrate to face a top surface of the first substrate, upper chip pads and an upper dummy pad on the top surface of the first substrate, penetration electrodes, which each penetrate the first substrate and are connected to separate, respective upper chip pads, lower chip pads on a bottom surface of the semiconductor device layer and electrically connected to separate, respective upper chip pads, and a lower dummy pad on the bottom surface of the semiconductor device layer and electrically isolated from the upper dummy pad. A distance between the upper and lower dummy pads in a horizontal direction that is parallel to the first substrate may be smaller than a diameter of the lower dummy pad.
1. A method of inspection of a semiconductor package, the method comprising:
preparing a first semiconductor chip including a first lower chip pad, a second lower chip pad and an upper dummy pad;
placing a second semiconductor chip including a lower dummy pad on the first semiconductor chip; and
measuring an alignment accuracy between the first semiconductor chip and the second semiconductor chip,
wherein the first and second lower chip pads are located on a bottom surface of the first semiconductor chip and spaced apart from each other,
wherein the upper dummy pad is located on a top surface of the first semiconductor chip and connected to the second lower chip pad,
wherein the lower dummy pad is located on a bottom surface of the second semiconductor chip and connected to the first lower chip pad, and
wherein measuring the alignment accuracy includes measuring whether the lower dummy pad and the upper dummy pad are electrically connected.
2. The method of claim 1 , wherein measuring whether the lower dummy pad and the upper dummy pad are electrically connected is measuring resistance between the first lower chip pad and the second lower chip pad.
3. The method of claim 1 , wherein measuring whether the lower dummy pad and the upper dummy pad are electrically connected is applying a voltage to the first lower chip pad and measuring an output voltage from the second lower chip pad.
4. The method of claim 1 , wherein
the first semiconductor chip further includes penetrating electrodes, and
wherein the upper dummy pad is connected to the second lower chip pad through one of the penetrating electrodes.
5. The method of claim 1 , wherein
the second semiconductor chip further includes a conductive line, and
the lower dummy pad is connected to the first lower chip pad through the conductive line.
6. The method of claim 1 , wherein a bump is located on a bottom surface of the lower dummy pad.
7. The method of claim 1 , wherein a diameter of the upper dummy pad is smaller than a diameter of the lower dummy pad.
8. The method of claim 1 , wherein a horizontal distance between the upper dummy pad and the lower dummy pad is smaller than a diameter of the lower dummy pad.
9. The method of claim 1 , wherein the upper dummy pad and the lower dummy pad are spaced apart from each other in a vertical direction.
10. The method of claim 1 , further comprising:
forming an insulating layer between the first semiconductor chip and the second semiconductor chip prior to measuring the alignment accuracy.
11. The method of claim 1 , wherein a horizontal distance between the upper dummy pad and the lower dummy pad is 3 μm to 20 μm.
12. The method of claim 1 , wherein a horizontal distance between the upper dummy pad and the lower dummy pad is greater than 0.3 and less than 1.0 of a diameter of the upper dummy pad or the lower dummy pad.
13. A method of inspection of a semiconductor package, the method comprising:
preparing a first semiconductor chip including first to third upper dummy pads;
mounting a second semiconductor chip including first to third lower dummy pads on the first semiconductor chip; and
measuring a misalignment between the first semiconductor chip and the second semiconductor chip,
wherein the first upper dummy pad and the first lower dummy pad, the second upper dummy pad and the second lower dummy pad, and the third upper dummy pad and the third lower dummy pad are adjacent to each other, and
wherein measuring the misalignment is respectively measuring whether an electrical connection between the first to third upper dummy pads and the first to third lower dummy pads.
14. The method of claim 13 , wherein
a first horizontal distance between the first upper dummy pad and the first lower dummy pad is smaller than a second horizontal distance between the second upper dummy pad and the second lower dummy pad and a third horizontal distance between the third upper dummy pad and the third lower dummy pad, and
the third horizontal distance is greater than the first horizontal distance and the second horizontal distance.
15. The method of claim 14 , wherein
the second upper dummy pad and the second lower dummy pad are electrically connected, and the third upper dummy pad and the third lower dummy pad are electrically insulated from each other, and
the misalignment is greater than the second horizontal distance and less than the third horizontal distance.
16. The method of claim 13 , wherein the first to third upper dummy pads are on a top surface of the first semiconductor chip.
17. The method of claim 13 , wherein the first to third lower dummy pads are on a bottom surface of the second semiconductor chip.