Semiconductor device including standard cells

1. A semiconductor device including a plurality of standard cells, wherein:

the plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction, and a third standard cell,

the first group of standard cells and the second group of standard cells are arranged in a column direction,

a first cell height of the first group of standard cells in the column direction is different from a second cell height of the second group of standard cells, and

the third standard cell is disposed over the first row and the second row and has a cell height equal to a sum of the first cell height and the second cell height.

2. The semiconductor device of claim 1 , wherein:

each of the plurality of standard cells includes a first power supply wiring for supplying first potential and a second power supply wiring for supplying second potential different from the first potential, and

a cell height of each of the plurality of standard cells is a distance in the column direction between a center line, extending in the row direction, of the first power supply wiring and a center line, extending in the row direction, of the second power supply wiring.

3. The semiconductor device of claim 2 , wherein a ratio of the first cell height of the first group of standard cells and the second cell height of the second group of standard cells is N:M, where N and M are different natural number.

4. The semiconductor device of claim 2 , wherein one of the first power supply wiring and the second power supply wiring of the first group of standard cells is shared by the second group of standard cells.

5. The semiconductor device of claim 4 , wherein each of the plurality of standard cells includes active fin structures extending in the row direction, and forming one or more fin field effect transistors (FinFETs).

6. The semiconductor device of claim 5 , wherein in the first group of standard cells, the active fin structures are aligned with either one of only I virtual lines extending in the row direction, respectively, where I is a natural number of two or more.

7. The semiconductor device of claim 6 , wherein in the second group of standard cells, the active fin structures are aligned with either one of only J virtual lines extending in the row direction, respectively, where J is a natural number of two or more different from I.

8. The semiconductor device of claim 7 , wherein either of I or J is two.

9. The semiconductor device of claim 5 , wherein each of the plurality of standard cells further includes one or more dummy fin structures extending in the row direction, and not functioning as a FinFET.

10. The semiconductor device of claim 9 , wherein:

one of the one or more dummy fin structures is located between two of the active fin structures, and

the one of the one or more dummy fin structures and the two of the active fin structures are arranged with a constant pitch in the column direction.

11. The semiconductor device of claim 5 , wherein:

each of the plurality of standard cells further includes dummy fin structures extending in the row direction, and not functioning as a FinFET, and

one of the dummy fin structures is located under the first power supply wiring, and one of the dummy fin structures is located under the second power supply wiring.

12. The semiconductor device of claim 11 , wherein at least one of a height and a width of the dummy fin structures is different from that of the active fin structures.

13. A semiconductor device including a plurality of standard cells, wherein:

the plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction, a second group of standard cells arranged in a second row extending in the row direction, and a third group of standard cells arranged in a third row extending in the row direction,

the first group of standard cells, the second group of standard cells and the third group of standard cells are arranged in a column direction, and

at least two of a first cell height of the first group of standard cells in the column direction, a second cell height of the second group of standard cells in the column direction and a third cell height of the third group of standard cells in the column direction are different from each other.

14. The semiconductor device of claim 13 , wherein:

the first cell height of the first group of standard cells, the second cell height of the second group of standard cells and the third cell height of the third group of standard cells are determined based on a number of fin structures arranged along the column direction within each of plurality of standard cells.

15. The semiconductor device of claim 14 , wherein:

each of the plurality of standard cells includes a first power supply wiring for supplying first potential and a second power supply wiring for supplying second potential different from the first potential, and

a cell height of each of the plurality of standard cells is a distance in the column direction between a center line, extending in the row direction, of the first power supply wiring and a center line, extending in the row direction, of the second power supply wiring.

16. The semiconductor device of claim 15 , wherein:

the plurality of standard cells include a fourth standard cell, and

the fourth standard cell is disposed over at least two rows adjacent to each other.

17. A semiconductor device including a plurality of standard cells, wherein:

the plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction, a second group of standard cells arranged in a second row extending in the row direction, and a third group of standard cells arranged in a third row extending in the row direction,

the first group of standard cells, the second group of standard cells and the third group of standard cells are arranged in a column direction,

at least two of a first cell height of the first group of standard cells in the column direction, a second cell height of the second group of standard cells in the column direction and a third cell height of the third group of standard cells in the column direction are different from each other, and

the first cell height of the first group of standard cells, the second cell height of the second group of standard cells and the third cell height of the third group of standard cells are determined based on a number of metal wirings arranged along the column direction within each of plurality of standard cells, the metal wirings being located at a level closer to a substrate than a level at which the first and second power supply wirings are located.

18. The semiconductor device of claim 17 , wherein the first cell height of the first group of standard cells, the second cell height of the second group of standard cells and the third cell height of the third group of standard cells are different from each other.

19. The semiconductor device of claim 17 , wherein:

the plurality of standard cells include a fourth standard cell, and

the fourth standard cell is disposed over at least two rows adjacent to each other.

20. The semiconductor device of claim 19 , wherein the fourth standard cell is disposed over three adjacent to each other.