IP Library Granted Patent US 11,935,898
Granted Patent B2
US 11,935,898 · App. 17/031,999 · Granted Mar 19, 2024

Semiconductor device and display device

Inventors: Tatsuya Toda (Tokyo, JP); Toshinari Sasaki (Tokyo, JP); Masayoshi Fuchi (Tokyo, JP)
Assignee: Japan Display Inc.
H01L27/124G02F1/136227G02F1/136286G02F1/1368G09G3/3225G09G3/3266H01L27/1259H10K59/123H10K59/124H10K59/131G02F1/136295G09G2300/0861H01L27/1225H01L27/1255H10K59/1201
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Quick Facts
Patent No.
US 11,935,898
App. No.
17/031,999
Granted
Mar 19, 2024
Kind
B2
Abstract

A semiconductor device including: a first gate electrode; a first gate insulating layer on the first gate electrode; a first oxide semiconductor layer on the first insulating layer; source and drain electrodes connected to the first oxide semiconductor layer; a second gate insulating layer on the first oxide semiconductor layer; a second oxide semiconductor layer on the second gate insulating layer; a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer; a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping with the second oxide semiconductor layer in a planar view; and a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.

Claims (53)

1. A semiconductor device comprising:

a first gate electrode;

a first gate insulating layer on the first gate electrode;

a first oxide semiconductor layer on the first gate insulating layer;

source and drain electrodes connected to the first oxide semiconductor layer;

a second gate insulating layer on the first oxide semiconductor layer;

a second oxide semiconductor layer on the second gate insulating layer;

a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer;

a first insulating layer on the second gate electrode, the first insulating layer having a part of a first aperture overlapping the second oxide semiconductor layer in a planar view; and

a first connecting electrode electrically connecting the first gate electrode and the second gate electrode via the first aperture.

2. The semiconductor device according to claim 1 , wherein the first connecting electrode covers a side surface of the second oxide semiconductor layer in the first aperture.

3. The semiconductor device according to claim 2 , further comprising a second connecting electrode arranged in the same layer with the source and drain electrodes,

wherein

the source and drain electrodes is in contact with the first oxide semiconductor layer from upper of the first oxide semiconductor layer,

the first gate insulating layer has a second aperture reaching to the first gate electrode,

the second connecting electrode is connected to the first gate electrode via the second aperture,

a part of the first aperture reaching to the second connecting electrode is arranged in the second gate insulating layer, and

the first connecting electrode is connected to the second connecting electrode via the first aperture.

4. The semiconductor device according to claim 2 , wherein a region of the second oxide semiconductor layer overlapping the part of the first aperture in a planar view is exposed from the second gate electrode and is in contact with the first connecting electrode.

5. A display device comprising:

a first gate electrode;

a first gate insulating layer on the first gate electrode;

a first oxide semiconductor layer on the first gate insulating layer;

source and drain electrodes connected to the first oxide semiconductor layer;

a second gate insulating layer on the first oxide semiconductor layer, the second gate insulating layer having a part of a third aperture;

a second oxide semiconductor layer on the second gate insulating layer;

a second gate electrode on the second oxide semiconductor layer, the second gate electrode being in contact with the second oxide semiconductor layer;

a first insulating layer on the second gate electrode, the first insulating layer having another part of the third aperture;

a third connecting electrode on the first insulating layer, the third connecting electrode being connected to one of the source and drain electrodes via the third aperture;

a second insulating layer on the third connecting electrode, the second insulating layer having a fourth aperture; and

a pixel electrode on the second insulating layer, the pixel electrode being connected to the third connecting electrode via the fourth aperture;

wherein

the first gate electrode and the one of the source and drain electrodes overlap each other in a planar view,

the one of the source and drain electrodes and the second gate electrode overlap each other in a planar view, and

the second gate electrode and the third connecting electrode overlap each other in a planar view.

6. The display device according to claim 5 , further comprising:

a driver transistor having a channel made of the first oxide semiconductor layer; and

a selection transistor connected to the driver transistor;

wherein

the driver transistor further comprises first and second connecting electrodes connecting the first gate electrode and the second gate electrode,

a drain electrode of the selection transistor is connected to the first and second connecting electrodes.

7. The display device according to claim 6 , wherein

the second gate insulating layer and the first insulating layer have a first aperture overlapping the second oxide semiconductor layer and the drain electrode of the selection transistor, and

the first connecting electrode electrically connects the second gate electrode and the drain electrode of the selection transistor via the first aperture.

8. The display device according to claim 7 , wherein the first connecting electrode covers a side surface of the second oxide semiconductor layer in the first aperture.

9. The display device according to claim 8 , wherein

the source and drain electrodes is in contact with the first oxide semiconductor layer from upper of the first oxide semiconductor layer,

the first gate insulating layer has a second aperture reaching to the first gate electrode, and

the second connecting electrode is connected to the first gate electrode via the second aperture.

10. The display device according to claim 7 , wherein a region of the second oxide semiconductor layer overlapping the first aperture in a planar view is exposed from the second gate electrode and is in contact with the first connecting electrode.

11. The display device according to claim 5 , wherein the second oxide semiconductor layer is a crystalline oxide semiconductor.

12. The display device according to claim 5 , wherein a crystallizability of the second oxide semiconductor layer is higher than a crystallizability of the first oxide semiconductor layer.

13. The display device according to claim 5 , wherein an oxygen content of the second oxide semiconductor layer is larger than an oxygen content of the first oxide semiconductor layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: TODA, TATSUYA; SASAKI, TOSHINARI; FUCHI, MASAYOSHI
To: JAPAN DISPLAY INC.
Reel/Frame 054241/0452 →
Priority Claims (1)
JP 2018-067326 · Mar 30, 2018 · national
Continuity (2)
Continuation PCTJP2019007661 · Feb 27, 2019
Related Publication 20210013235A1 · Jan 14, 2021