Geometry for threshold voltage tuning on semiconductor device
Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
1. A method for semiconductor processing, the method comprising:
etching trenches in a substrate to define a first fin and a second fin;
recessing the second fin;
forming a first isolation region adjacent the first fin, wherein the first fin extends above the first isolation region by a first distance;
forming a second isolation region adjacent the second fin, wherein the second fin extends above the second isolation region by a second distance, wherein the first distance is greater than the second distance; and
forming a first gate structure over the first fin and a second gate structure over the second fin, wherein a third distance from an upper surface of the first fin to an upper surface of the first gate structure is less than a fourth distance from an upper surface of the second fin to an upper surface of the second gate structure.
2. The method of claim 1 , wherein the first gate structure comprises a first dummy gate structure, wherein the second gate structure comprises a second dummy gate structure, further comprising:
replacing the first gate structure with a first replacement gate structure; and
replacing the second gate structure with a second replacement gate structure, wherein a fifth distance from the upper surface of the first fin to an upper surface of the first replacement gate structure is less than a sixth distance from the upper surface of the second fin to an upper surface of the second replacement gate structure.
3. The method of claim 2 , wherein the upper surface of the first replacement gate structure is level with the upper surface of the second replacement gate structure.
4. The method of claim 2 , wherein the first replacement gate structure and the second replacement gate structure comprises a same one or more conductive layers.
5. The method of claim 4 , wherein the first replacement gate structure and the second replacement gate structure have different threshold voltages.
6. The method of claim 1 , wherein forming the first isolation region and the second isolation region comprises:
forming one or more layers of dielectric material adjacent the first fin and the second fin prior to recessing the second fin; and
recessing the one or more layers of dielectric material after recessing the second fin to form the first isolation region and the second isolation region.
7. The method of claim 1 , wherein recessing the second fin comprises a wet etch process.
8. A method for semiconductor processing, the method comprising:
forming a first fin and a second fin protruding above a first isolation region, wherein the first fin protrudes above the first isolation region a first distance, wherein the second fin protrudes above the first isolation region a second distance, wherein the first distance is greater than the second distance, wherein a height of the first fin is different than a height of the second fin, wherein forming the first fin and the second fin comprises:
etching trenches in a substrate to define the first fin and the second fin;
depositing one or more dielectric layers in the trenches, wherein an upper surface of the first fin and an upper surface of the second fin are exposed;
forming a mask over the first fin;
recessing the second fin below an upper surface of the one or more dielectric layers; and
recessing the one or more dielectric layers to form the first isolation region;
forming a first gate structure over the first fin; and
forming a second gate structure over the second fin, wherein an upper surface of the first gate structure is level with an upper surface of the second gate structure.
9. The method of claim 8 , wherein the first gate structure and the second gate structure are dummy gate structures, and further comprising replacing at least portions of the first gate structure and the second gate structure with a first replacement gate structure and a second replacement gate structure.
10. The method of claim 9 , wherein the first replacement gate structure and the second replacement gate structure comprises a same one or more conductive layers.
11. The method of claim 10 , wherein the first replacement gate structure is associated with a first threshold voltage, and wherein the second replacement gate structure is associated with a second threshold voltage, wherein the second threshold voltage is different than the first threshold voltage.
12. The method of claim 9 , wherein an upper surface of the first replacement gate structure is level with an upper surface of the second replacement gate structure.
13. The method of claim 12 , further comprising forming a second isolation region over the first isolation region, wherein the upper surface of the first replacement gate structure is level with an upper surface of the second isolation region.
14. The method of claim 8 , wherein the first gate structure comprises a first gate electrode, wherein the first gate electrode has a first thickness over the first fin, the second gate structure comprises a second gate electrode, wherein the second gate electrode has a second thickness over the second fin, wherein the first thickness is different than the second thickness.
15. A method for semiconductor processing, the method comprising:
forming a first fin and a second fin protruding from a substrate and extending through a first isolation region, wherein the first fin has a greater height above the first isolation region than the second fin;
forming a first dummy gate structure over the first fin and a second dummy gate structure over the second fin;
forming a second isolation region on opposing sides of the first dummy gate structure and the second dummy gate structure;
removing the first dummy gate structure to expose the first fin and removing the second dummy gate structure to expose the second fin; and
forming a first replacement gate structure over the first fin and a second gate replacement structure over the second fin, wherein the first replacement gate structure has a first distance from an end of the first replacement gate structure to the first fin, wherein the second replacement gate structure has a second distance from an end of the second replacement gate structure to the second fin, wherein the first distance is different than the second distance, wherein the first fin is a closest first fin to the end of the first replacement gate structure, wherein the second fin is a closest second fin to the end of the second replacement gate structure.
16. The method of claim 15 , wherein an upper surface of the first replacement gate structure is level with an upper surface of the second replacement gate structure.
17. The method of claim 15 , wherein forming the first fin and forming the second fin comprises:
forming the first fin and the second fin protruding from the substrate;
forming one or more layers of dielectric material adjacent the first fin and the second fin, wherein an upper surface of the second fin is exposed;
recessing the second fin below an upper surface of the one or more layers of dielectric material; and
recessing the one or more layers of dielectric material, thereby forming the first isolation region.
18. The method of claim 17 , wherein forming the first fin and the second fin comprises forming trenches in the substrate.
19. The method of claim 15 , wherein a thickness of the first replacement gate structure over the first fin is different than a thickness of the second replacement gate structure over the second fin.